SUMMIT
MICROELECTRONICS, Inc.
SMS8198
Philips TriMedia™ Processor Companion Supervisor
With a 16K-bit 2-wire Serial Memory
FEATURES
• Designed to operate with the Philips
TriMedia Processor
• Coordinating the System Reset Function and
Providing the Processor’s Configuration
Memory
• Multiple V
TRIP
Thresholds
- No External Components Required
•
Guaranteed Reset Assertion to V
CC
-1V
• Reset is an I/O
- Allows System Reset Clean up
- Provides a De-bounced Manual Reset Func-
tion
• Industry Standard 2-wire Serial Interface
• Hardware Write Lockout Function
• High Reliability
- Endurance: 100,000 write cycles
- Data Retention: 100 Years
OVERVIEW
The SMS8198 is a precision supervisory circuit designed
specifically as a companion chip for the Philips TriMedia
Processor family. The SMS8198 monitors the power
supply and holds the system in reset whenever V
CC
is
below the V
TRIP
threshold.
In addition to the supervisory function, the SMS8198 has
16K-bits of nonvolatile memory that is used by the
TriMedia processor as the boot memory.
The SMS8198 provides 16K-bits of memory that is acces-
sible through the industry standard 2-wire serial interface.
By integrating a precision supervisory circuit and the
hardware WP input, the SMS8198 becomes the perfect
companion chip for the Philips TriMedia processor family.
Its functions are integral to the boot hardware operation of
the TriMedia processors.
BLOCK DIAGRAM
VCC
8
SCL
SDA
6
5
NONVOLATILE
MEMORY
ARRAY
WRITE
CONTROL
7
WP
2
PROGRAMMABLE
RESET PULSE
GENERATOR
TRI_RESET#
+
–
VTRIP
RESET
CONTROL
1.26V
4
GND
SUMMIT MICROELECTRONICS, Inc.
•
300 Orchard City Drive, Suite 131
•
Campbell, CA 95008
•
2036 T BD 2.0
Telephone 408-378-6461
•
Fax 408-378-6586
•
www.summitmicro.com
© SUMMIT MICROELECTRONICS, Inc. 2000
2036 5.0 4/18/00
Characteristics subject to change without notice
1
SMS8198
Camera
Audio
4.7K
10K
4.7K
4.7K
Tri Media
Processor
WP
TRI_RESET#
TRI_RESET#
VCR/Monitor
Audio
SCL
SDA
System Boot
Block
SMS8198
Local Reset
Peripheral
Peripheral
PCI_RESET#
PCI Bus
2036 ILL16.0
Figure 1. Typical Implementation of the SMS8198 and TriMedia Processor
The boot hardware operation begins with the assertion of
the reset signal TRI_RESET#. The TRI_RESET# output
from the SMS8198 is guaranteed to be valid at V
CC
-1.0V.
The reset output is asserted whenever V
CC
is less than the
V
TRIP
threshold and will remain asserted after V
CC
is
>V
TRIP
for the duration of t
PURST
. Whenever the
TRI_RESET# is active the memory will be write protected.
In addition to the reset write protection feature, pin 7 can
be tied to a pull-up to disable the write function of the
memory. This effectively turns the memory array into an
inexpensive boot ROM.
After reset is de-asserted, only the system boot block is
allowed to operate. At this point the TriMedia processor
takes over and begins to download data from the memory
array into its system boot block. The data downloaded
contains configuration data to set up the TriMedia proces-
sor and to load special ID information into the PCI configu-
ration space register. The ID information is published in
the PCI configuration register to provide the 16 bit Sub-
system ID and Subsystem Vendor ID.
It should be noted that both the threshold and the t
PURST
pulse width are programmable. Not only does this provide
maximum flexibility to the designer, but, as the processor
operating voltage levels migrate downwards, the
SMS8198 can be programmed to following this downward
trend. The values can be selected from the ordering
information table and the devices specified as standard
off-the-shelf items.
2036 5.0 4/18/00
2
SMS8198
tGLITCH
VTRIP
VRVALID
tRPD
tPURST
tPURST
VCC
TRI_RESET#
tRPD
2036 T fig02 2.0
Figure 2. Reset Output Timing
RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS
T
A
= -40°C to +85°C
Symbol
VTRIP
Parameter
Reset Trip Point
Part no. Suffix
A (or) Blank
B
2.7
tPURST
tRPD
VRVALID
tGLITCH
VOLRS
VOHRS
Reset Timeout
VTRIP to RESET Output Delay
RESET Output Valid to VCC min. Guarantee
Glitch Reject Pulse Width note 1
RESET Output Low Voltage IOL = 1mA
RESET High Voltage Output IOH = 800µA
Min.
4.250
4.50
2.55
Typ.
4.375
4.625
2.65
200
5
1
30
0.4
Max.
4.5
4.75
2.75
Unit
V
V
V
ms
µs
V
ns
V
2036 5.0 4/18/00
3
SMS8198
PIN CONFIGURATIONS
TRI_RESET#
- is an active low open drain output. It is
driven low whenever V
CC
is below V
TRIP
. TRI_RESET# is
also an input and can be used to debounce a switch input
or perform signal conditioning. The TRI_RESET# pin
does have an internal pull-up and should be left uncon-
nected if the signal is not used in the system. However,
when the pin is tied to a system TRI_RESET# line an
external pull-up resistor should be employed.
Write Protect (WP)
- All write operations can be disabled
by maintaining WP > V
IH
.
No Connects (NC)
- The no connect inputs are unused by
the SMS8198; however, to insure proper operation they
can be unconnected or tied to ground. They must not be
tied to V
CC
.
ENDURANCE AND DATA RETENTION
PIN NAMES
SDA
SCL
TRI_RESET#
GND
V
CC
WP
NC
Serial Data I/O
Serial Clock Input
Reset Output
Ground
Supply Voltage
Write Protect
No Connect
The SMS8198 is designed for applications requiring up to
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
RESET CONTROLLER DESCRIPTION
The device provides a precise reset output to a
microcontroller and it’s associated circuitry ensuring cor-
rect system operation during power-up/down conditions
and brownout situations. The output is open drain, allow-
ing control of the reset function by multiple devices.
During power-up the reset output remains in a fixed active
state until V
CC
passes through the reset threshold and
remains above the threshold for t
PURST
. The reset output
is valid whenever V
CC
is equal to or greater than 1V. If V
CC
falls below the threshold for more than t
GLITCH
the device
will immediately generate a reset and drive the output.
The reset pin is an I/O; therefore, forcing the pin to the
active state can also manually reset the device. Because
the I/O needs to be an open drain, the internal timer can
only be triggered by the leading edge of the input. The
resulting reset output will either be t
PURST
, or the externally
applied reset signal, whichever is longer. This can provide
an affective debounce or reset signal extender solution.
8-Pin SOIC
NC
TRI_RESET#
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
2036 T PCon 2.0
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
2036 5.0 4/18/00
4
SMS8198
SCL
Data must
remain stable
while clock
is HIGH.
Change
of data
allowed
Data must
remain stable
while clock
is HIGH.
SDA In
t
HD:DAT
t
SU:DAT
t
HD:DAT
2036 ILL4.0
Figure 3. Input Data Protocol
SCL from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Condition
1
8
9
t
AA
t
AA
ACKnowledge
2036 ILL6.0
Figure 4. Acknowledge Response From Receiver
2036 5.0 4/18/00
5
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