MA009A
24-bit I/O extender with interrupt function
Features
•
Operation voltage: 2.0V to 5.7V
•
Low standby current (1uA, typ.)
•
2 Mbps, 3-wire serial interface
•
8 chip addresses are provided
•
24 input/output pins
Selection Information
Package / Dice
Parallel Input
Parallel Output
Parallel I/O
Max. Sink Current
MA009AH
Dice
MA009AP
44-PLCC
♦
16 input pins with pull-high disable/enable
and interrupt function
♦
16 output pins with CMOS/NMOS,
large/small sink capability
MA009AD
48-LQFP
8 pins
8 pins
8 pins
20mA
MA009AF
44-PQFP
Application Field
System I/O port
LED status indicator
This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue
this product without notice.
©
MEGAWIN Technology Co., Ltd. 2006 All rights reserved.
2006/09 version A1
MEGAWIN
General Description
The MA009 is high-speed Si-gate CMOS devices
that provide a general purpose I/O peripheral. The
MA009 provides microcontroller eight input pins
plus eight I/O pins and eight output pins. Each
input pin can be configured as interrupt source and
output pin can be configured as CMOS/NMOS
output. The MA009 is controlled through a 3-wire
serial interface, and can be set as one of eight chip
addresses by pin option.
The device is optimized
for use in many commercial and industrial
applications where high density, low pin count,
low voltage, and low power are essential.
Pad Description
Pad No.
1, 8, 9
2, 3, 4
5
6
7
10
20 to 13
29 to 22
38 to 31
Pad Name
NC
A0, A1, A2
C/DB
SCLK
Sin
INTB
P
20
to P
27
P
10
to P
17
P
00
to P
07
V
CC
GND
12, 30, 40, 41
11, 21, 39
I/O
I
I
I
I
I
O
O
O
O
P
P
Description
No connection
Chip Address bit0, bit1, bit2
Serial interface, command/data selector
Serial interface, serial clock
Serial interface, serial command/data input
Input port interrupt event indicator
Output Port 2
Input/Output Port 1
Input Port 0
Positive supply voltage
Power ground (0 V)
2
MA009A Technical Summary
MEGAWIN
Block Diagram
C/DB
SCLK
Sin
Serial to
Parallel
Converting
Logic
Control
Logic
Input Port
P0
P0
I/O Port
P1
P1
Output Port
P2
P2
INTB
A0 ~ A2
Vdd
Vss
MEGAWIN
MA009A Technical Summary
3
Function Description
There are three 8-bit I/O ports (P0 is pure input port, P1 is I/O port and P2 is pure output port) and one
interrupt output pin (INTB) in MA009. The MA009 operates as a slave that sends and receives data
through a 3-wire interface. The interface uses a command/data select line (C/DB); serial
command/data line (Sin) and a serial clock line (SCLK) to achieve bidirectional communication
between master(s) and slave(s). The master (such as microcontroller) should send serial clock and
serial command to configure or to get data from MA009. The serial communication waveform are
shown as below:
COMMAND WRITE PERIOD
COMMAND
DATA
C/DB
SCLK
Sin
MSB
LSB
Command Write Period Waveform (command should be ready in rising edge)
COMMAND READ PERIOD
COMMAND
DATA
C/DB
SCLK
Sin
MSB
LSB
Command Read Period Waveform (master can get data in falling edge)
4
MA009A Technical Summary
MEGAWIN
Control Registers Definition
The default value of all the control register is 0 after power on.
Chip Address
Name
C_ADDR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
A02
Bit 1
A01
Bit 0
A00
Chip address register.
Only the contents of chip address register are same as chip address pin A2, A1 and A0, all command could be
enabled. This function will make the master to connect more than one MA009 easily.
Input Port 0
Name
P0
Bit 7
P07
Bit 6
P06
Bit 5
P05
Bit 4
P04
Bit 3
P03
Bit 2
P02
Bit 1
P01
Bit 0
P00
Port P0 input status register.
Name
P0PR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
PR01
Bit 0
PR00
Port P0 pull high control register.
P0PR.0: P0.0 ~ P0.3 pull high control, 0: enable (large resistance, 350K), 1: disable
P0PR.1: P0.4 ~ P0.7 pull high control, 0: enable (large resistance, 350K), 1: disable
Name
P0PSR
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
PS01
Bit 0
PS00
Port P0 strong pull high selection register.
P0PSR.0: P0.0 ~ P0.3 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
P0PSR.1: P0.4 ~ P0.7 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
Name
P0IEN
Bit 7
IE07
Bit 6
IE06
Bit 5
IE05
Bit 4
IE04
Bit 3
IE03
Bit 2
IE02
Bit 1
IE01
Bit 0
IE00
Port P0 interrupts enable register.
P0IEN.0 ~ P0IEN.7: P0.0 ~ P0.7 falling edge interrupts control, 0: disable, 1: enable
Name
P0EVT
Bit 7
ST07
Bit 6
ST06
Bit 5
ST05
Bit 4
ST04
Bit 3
ST03
Bit 2
ST02
Bit 1
ST01
Bit 0
ST00
Port P0 interrupts events status register.
When a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of P0IEN is set to 1) pins of port P0,
the corresponding bit of P0EVT will be set to 1. The interrupt will be generated from the INTB (1!0) pin in this
condition, and the mater (for example, a microcontroller) can read the interrupt status from P0EVT. The master
can send EVTCLR (13H) command to MA009 to clear the P0EVT after the interrupt event is processed. This
MEGAWIN
MA009A Technical Summary
5
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