(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
FEATURES
•
•
•
Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for
all frequencies
.
Less than 25ps (typ.) peak to peak jitter for all
frequencies.
Low phase noise output (@ 1MHz frequency
offset
∗
-144dBc/Hz for 155.52MHz
∗
-140dBC/Hz for 311.04MHz
19MHz-40MHz crystal input.
38MHz-320MHz output.
Available in PECL, LVDS, or CMOS outputs.
No external varicap required.
Output Enable selector.
Wide pull range (+/-200ppm).
3.3V operation.
Available in 3x3 QFN or 16-pin TSSOP
packages.
PACKAGE PIN ASSIGNMENT
VDDANA
XIN
XOUT
SEL2^
OE_CTRL
VCON
GNDANA
LP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL0^
SEL1^
GNDBUF
QBAR
VDDBUF
Q
GNDBUF
LM
PL580-3X
•
•
•
•
•
•
•
•
16-pin TSSOP
VDDANA
SEL0^
10
XOUT
12
13
14
15
16
1
11
SEL1^
9
XIN
8
7
6
GNDBUF
QBAR
VDDBUF
Q
DESCRIPTION
The PL580-3X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and CMOS, LVDS, or PECL outputs, covering a
wide frequency output range up to 320MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
The frequency selector pads of PL580-3X enable
output frequencies of (2, 4, 8, or 16) * F
XIN
. The
PL580-3X is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, Video, etc.
SEL2^
OE_CTRL
VCON
PL580-3X
2
3
4
5
GNDANA
3x3 QFN
Note1: QBAR is used for single ended CMOS output
.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCON
VARICAP
VCO
Divider
Charge
Pump
+
Loop
Filter
Output
Divider
(1,2,4,8)
GNDBUF
LP
LM
XIN
XOUT
XTAL
OSC
Phase
Detector
VCO
(F
XiN
x16)
QBAR
Q
Performance Tuner
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 1
(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
OUTPUT ENABLE LOGICAL LEVELS
Part #
PL580-38 (PECL)
PL580-35 (PECL)
PL580-37 (CMOS)
PL580-39 (LVDS)
OE
0 (Default)
1
0
1 (Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
PIN DESCRIPTIONS
Name
VDDANA
XIN
XOUT
SEL2
OE_CTRL
VCON
GNDANA
LP
LM
GNDBUF
Q
VDDBUF
QBAR
GNDBUF
SEL1
SEL0
TSSOP
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3x3mm QFN
Pin number
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
Type
P
I
O
I
I
I
P
-
-
P
O
P
O
P
I
I
VDD for analog Circuitry.
Description
Crystal input pin. (See Crystal Specifications on page 4).
Crystal output pin. (See Crystal Specifications on page 4).
Output frequency Selector pin.
Output enable control pin. (See OE_CTRL Logic Levels).
Voltage control input.
Ground for analog circuitry.
Tuning inductor connection. The inductor is recommended to be
a high Q small size 0402 or 0603 SMD component, and must be
placed between LP and adjacent LM pin. Place inductor as close
to the IC as possible to minimize parasitic effects and to
maintain inductor Q.
GND connection for output buffer circuitry.
PECL or LVDS output.
VDD connection for output buffer circuitry. VDDBUF should be
separately decoupled from other VDDs whenever possible.
Complementary PECL, LVDS, Or single ended CMOS output.
GND connection for output buffer circuitry.
Output frequency Selector pin.
Output frequency Selector pin.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 2
(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
FREQUENCY SELECTION TABLE
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Selected Multiplier/Output Frequency
VCO Max*
VCO Min*
Reserved
Reserved
Fin x 2
Fin x 8
Fin x 16
Fin x 4
All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0.
* Special Test Modes to help selecting the inductor value for the target output frequency.
PERFORMANCE TUNING & INDUCTOR VALUE SELECTION
Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor
values for your application. In addition, the chart below could be used as a reference for quick inductor value
selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning
Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance
enhancement of your custom board design, please follow the following instruction:
Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max”
represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output
frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are
around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency
is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock
in the middle of its tuning range with maximum margin on either side.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 3
(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
at VCON = 0V
at VCON = 1.65V
at VCON = 3.3V
AT cut
AT cut
MIN.
19
TYP.
17.7
9.5
5.4
MAX.
40
UNITS
MHz
pF
250
30
-
Ω
Note:
Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package
parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note,
that frequency pulling and oscillator gain may decrease.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 19 – 40MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
500
±200
150
10
60
25
80
0V
≤
VCON
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 4
(Preliminary)
PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
Note:
CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
38MHz<Fout<100MHz
100MHz<Fout<320MHz
MIN.
TYP.
MAX.
65/45/30
80/60/40
UNITS
mA
V
%
mA
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
2.97
45
45
45
50
50
50
±50
3.63
55
55
55
5. Jitter Specifications
PARAMETERS
Integrated jitter RMS
CONDITIONS
Integrated 12 kHz to 20 MHz
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
FREQUENCY
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
MIN.
TYP.
0.4
0.4
2.5
3
4
18
20
25
MAX.
0.5
0.5
4
5
7
30
30
35
UNITS
ps
Period jitter RMS
ps
Period jitter Peak-to-
Peak
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise
relative to
carrier (typical)
FREQ.
77.76MHz
155.52MHz
311.04MHz
@10Hz
-66
-62
-59
@100Hz
-96
-92
-86
@1kHz
-124
-120
-116
@10kHz
-134
-132
-129
@100kHz
-132
-128
-124
@1M
-145
-144
-140
@10M
-149
-150
-148
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V.
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP.
MAX.
UNITS
mA
mA
0.7
0.3
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/14/06 Page 5
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