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TN5335

产品描述N-channel enhancement-mode vertical dmos fets
文件大小441KB,共2页
制造商Supertex
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TN5335概述

N-channel enhancement-mode vertical dmos fets

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TN5335
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
350V
*
Same as SOT-89.
R
DS(ON)
(max)
15Ω
V
GS(th)
(max)
2.0V
I
D(ON)
(min)
750mA
Order Number / Package
TO-236AB
TN5335K1
TO-243AA*
TN5335N8
Wafer
TN5335NW
Product supplied on 2000 piece carrier tape reels.
Features
Low threshold – 2.0V max.
High input impedance
Low input capacitance
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Product marking for SOT-23
Product marking for TO-243AA
N3S❋
Where
= 2-week alpha date code
TN3S❋
Where
= 2-week alpha date code
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Modem hook switches
Package Options
D
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
11/12/01
D
G
G S
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
D
S
TO-236AB
(SOT-23)
top view
TO-243AA
(SOT-89)
Note: See Package Outline section for dimensions.
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1

TN5335相似产品对比

TN5335 TN5335NW TN5335N8 TN5335K1
描述 N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
是否Rohs认证 - 不符合 不符合 不符合
厂商名称 - Supertex Supertex Supertex
包装说明 - UNCASED CHIP, X-XUUC-N SMALL OUTLINE, R-PSSO-F3 SMALL OUTLINE, R-PDSO-G3
Reach Compliance Code - compliant compliant compliant
ECCN代码 - EAR99 EAR99 EAR99
其他特性 - HIGH INPUT IMPEDANCE LOGIC LEVEL COMPATIBLE HIGH INPUT IMPEDANCE
配置 - SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压 - 350 V 350 V 350 V
最大漏源导通电阻 - 15 Ω 15 Ω 15 Ω
FET 技术 - METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 代码 - X-XUUC-N R-PSSO-F3 R-PDSO-G3
JESD-609代码 - e0 e0 e0
元件数量 - 1 1 1
工作模式 - ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
封装主体材料 - UNSPECIFIED PLASTIC/EPOXY PLASTIC/EPOXY
封装形状 - UNSPECIFIED RECTANGULAR RECTANGULAR
封装形式 - UNCASED CHIP SMALL OUTLINE SMALL OUTLINE
峰值回流温度(摄氏度) - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
极性/信道类型 - N-CHANNEL N-CHANNEL N-CHANNEL
认证状态 - Not Qualified Not Qualified Not Qualified
表面贴装 - YES YES YES
端子面层 - TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 - NO LEAD FLAT GULL WING
端子位置 - UPPER SINGLE DUAL
处于峰值回流温度下的最长时间 - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
晶体管应用 - SWITCHING SWITCHING SWITCHING
晶体管元件材料 - SILICON SILICON SILICON

 
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