Low Charge Injection
8-Channel High Voltage Analog Switch
Ordering Information
Package Options
Operating
V
PP
40V to 80V
80V to 150V
V
PP
– V
NN
160V
160V
28-lead plastic
chip carrier
HV21716PJ
HV21816PJ
Die
HV21716X
HV21816X
ETE –
SOL
– OB
HV21716
HV21816
Features
■
HVCMOS
®
technology for high performance
■
Low charge injection
■
Very low quiescent power dissipation – 10µA
■
Output On-resistance typically 22 ohms
■
Low parasitic capacitances
■
DC to 10MHz analog signal frequency
■
-50dB typical output off isolation at 5MHz
■
CMOS logic circuitry for low power
■
Excellent noise immunity
■
On-chip shift register and latch logic circuitry
■
Flexible high voltage supplies
■
Surface mount package available
General Description
Not recommended for new designs. Please use HV20220 for
all new designs.
This device is a low charge injection 8-channel high-voltage ana-
log switch integrated circuit (IC) intended for use in applications
requiring high voltage switching controlled by low voltage control
signals, such as ultrasound imaging and printers. Input data is
shifted into an 8-bit shift register which can then be retained in an
8-bit latch. To reduce any possible clock feedthrough noise, Latch
Enable (LE) should be left high until all bits are clocked in. Using
HVCMOS technology, this switch combines high voltage bilateral
DMOS switches and low power CMOS logic to provide efficient
control of high voltage analog signals.
Absolute Maximum Ratings*
V
DD
logic power supply voltage
V
PP
- V
NN
supply voltage
V
PP
positive high voltage supply
V
NN
negative high voltage supply
Logic input voltages
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation
-0.5V to +18V
174V
-0.5V to +160V
+0.5V to -160V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65°C to +150°C
1.2W
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
13-66
HV21716/HV21816
AC Characteristics
Characteristics
Time to Turn Off V
SIG
*
Set Up Time Before LE Rises
Time Width of LE
Clock Delay Time to Data Out
Turn On Time
Turn Off Time
Off Isolation
Sym
min
t
SIG (OFF)
t
SD
t
WLE
t
DO
t
ON
t
OFF
KO
-30
-45
Clock Freq
Set Up Time Data to Clock
Hold Time Data from Clock
Switch Crosstalk
Off Capacitance SW to GND
On Capacitance SW to GND
Output Voltage Spike
f
CLK
t
SU
t
H
K
CR
C
SG(OFF)
C
SG(ON)
+V
SPK
–V
SPK
* Time required for analog signal to turn off before output switch turns off (critical timing).
0
°
C
max
min
0
150
150
175
3.0
5.0
-30
-45
5.0
15
35
-60
5.0
25
17
50
15
35
-60
5.0
25
150
150
+25
°
C
typ
max
min
+70
°
C
max
Units
ns
Test Conditions
150
150
175
3.0
5.0
-33
-50
5.0
8.0
-70
12
38
150
150
17
50
20
35
-60
5.0
25
17
50
-30
-45
5.0
190
3.0
5.0
ns
ns
ns
µs
µs
dB
dB
MHz
ns
ns
dB
pF
pF
mV
f = 5MHz,
50Ω load
0V, 1MHz
0V, 1MHz
V
PP
= +80V,
V
NN
= -80V,
R
L
= 50Ω
R
L
= 10KΩ
R
L
= 10KΩ
f = 5MHz,
1KΩ// 15pF load
f = 5MHz,
50Ω load
50% duty cycle
f
DATA
= f
CLK
/2
ETE –
SOL
– OB
Operating Conditions*
Device
Symbol
V
PP1, 3
V
NN1, 3
V
DD1, 3
V
IH
V
IL
V
SIG2
T
A
HV21716
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HV21816
Value
40V to 80V
80V to 150V
-10V to V
PP
-160V
10V to 15.5V
V
DD
-2.0V to V
DD
0V to 2.0V
V
NN
+10V to V
PP
-10
0°C to 70°C
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. V
SIG
must be V
NN
≤
V
SIG
≤
V
PP
or floating during power up/down transistion.
3. Rise and fall times of power supplies, V
DD,
V
PP,
and V
NN
should not be less than 1.0msec.
13-68
HV21716/HV21816
Logic Diagram
LATCHES
D
IN
D
LE
D
LE
D
LE
D
LE
8 BIT
SHIFT
REGISTER
D
LE
D
LE
D
LE
D
LE
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
CLK
SW1
SW2
SW3
SW4
SW5
D
OUT
SW6
SW7
V
NN
V
PP
V
DD
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
D1
D2
D3
D4
D5
D6
TE –
SOLE
– OB
LE
D7
LE SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L
L
L
L
L
L
L
L
L
L
L
L
L
L
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
Notes:
1. The eight switches operate
independently.
2. Serial data is clocked in on the L→ H
transition CLK.
3. The switches go to a state retaining
their present condition at the rising
edge of LE. When LE is low the shift
register data flows through the latch.
4. D
OUT
is high when switch 7 is on.
5. Shift register clockng has no effect on
the switch states if LE is H.
L
H
X
X
X
X
X
X
X
X
L
L
H
13-70
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