designed for digitizing high frequency, wide dynamic range
signals. The LTC2262-12 is perfect for demanding commu-
nications applications with AC performance that includes
70.5dB SNR and 88dB spurious free dynamic range (SFDR).
Ultralow jitter of 0.17ps
RMS
allows undersampling of IF
frequencies with excellent noise performance.
DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL
(typical) and no missing codes over temperature. The
transition noise is a low 0.3LSB
RMS
.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
70.5dB SNR
88dB SFDR
Low Power: 146mW
Single 1.8V Supply
CMOS, DDR CMOS or DDR LVDS Outputs
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full-Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
APPLICATIONS
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multi-Channel Data Acquisition
Nondestructive Testing
TYPICAL APPLICATION
1.8V
V
DD
1.2V
TO 1.8V
OV
DD
2-Tone FFT, f
IN
= 68MHz and 69MHz
0
–10
–20
–30
AMPLITUDE (dBFS)
–40
–50
–60
–70
–80
+
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D11
CMOS
•
OR
•
LVDS
•
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
GND
226212 TA01a
–90
–100
–110
–120
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
150MHz
CLOCK
226212 TA01b
226212p
1
LTC2262-12
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (V
DD
, OV
DD
) ....................... –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN–
,
PAR/SER, SENSE) (Note 3) ...........–0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range:
LTC2262C ................................................ 0°C to 70°C
LTC2262I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
PIN CONFIGURATIONS
D10_11
SENSE
FULL-RATE CMOS OUTPUT MODE
TOP VIEW
V
REF
DNC
V
CM
D11
D10
V
DD
D9
D8
OF
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
SENSE
D8_9
DNC
V
REF
DNC
DNC
DNC
30 D6_7
29 DNC
28 CLKOUT
+
27 CLKOUT
–
41
26 OV
DD
25 OGND
24 D4_5
23 DNC
22 D2_3
21 DNC
11 12 13 14 15 16 17 18 19 20
CS
DNC
DNC
SDO
SCK
SDI
D0_1
ENC
+
ENC
–
V
CM
V
DD
OF
40 39 38 37 36 35 34 33 32 31
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
11 12 13 14 15 16 17 18 19 20
CS
SDO
DNC
DNC
SCK
D0
ENC
+
ENC
–
SDI
D1
41
30 D7
29 D6
28 CLKOUT
+
27
CLKOUT
–
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
40 39 38 37 36 35 34 33 32 31
26 OV
DD
25 OGND
24 D5
23 D4
22 D3
21 D2
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
D10_11
+
D10_11
–
SENSE
D8_9
+
D0_1
–
D8_9
–
30 D6_7
+
29 D6_7
–
28 CLKOUT
+
27 CLKOUT
–
41
26 OV
DD
25 OGND
24 D4_5
+
23 D4_5
–
22 D2_3
+
21 D2_3
–
11 12 13 14 15 16 17 18 19 20
CS
SDO
DNC
ENC
+
ENC
–
DNC
SCK
SDI
D0_1
+
V
REF
V
CM
V
DD
OF
+
OF
–
40 39 38 37 36 35 34 33 32 31
A
IN+
1
A
IN–
2
GND 3
REFH 4
REFH 5
REFL 6
REFL 7
PAR/SER 8
V
DD
9
V
DD
10
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
226212p
2
LTC2262-12
ORDER INFORMATION
LEAD FREE FINISH
LTC2262CUJ-12#PBF
LTC2262IUJ-12#PBF
TAPE AND REEL
LTC2262CUJ-12#TRPBF
LTC2262IUJ-12#TRPBF
PART MARKING*
LTC2262UJ-12
LTC2262UJ-12
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Transition Noise
Internal Reference
External Reference
External Reference
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
l
l
l
l
MIN
12
–1
–0.4
–9
–1.5
TYP
±0.3
±0.1
±1.5
±1.5
±0.4
±20
±30
±10
0.3
MAX
1
0.4
9
1.5
UNITS
Bits
LSB
LSB
mV
%FS
%FS
μV/°C
ppm/°C
ppm/°C
LSB
RMS
ANALOG INPUT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 150Msps
0 < A
IN+
, A
IN–
< V
DD
, No Encode
0 < PAR/SER < V
DD
0.625V < SENSE < 1.3V
l
l
l
l
l
l
MIN
V
CM
– 100mV
0.625
–1
–3
–6
TYP
1 to 2
V
CM
1.250
185
MAX
V
CM
+ 100mV
1.300
1
3
6
UNITS
V
P-P
V
V
μA
μA
μA
μA
ns
ps
RMS
dB
MHz
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
Analog Input Leakage Current
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
External Voltage Reference Applied to SENSE External Reference Mode
0
0.17
80
Figure 6 Test Circuit
800
226212p
3
LTC2262-12
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
30MHz Input
70MHz Input
140MHz Input
5MHz Input
30MHz Input
70MHz Input
140MHz Input
l
DYNAMIC ACCURACY
MIN
TYP
70.5
70.4
70.3
70.1
88
88
82
81
90
90
90
90
70.4
70.3
70
69.8
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
l
Spurious Free Dynamic Range
4th Harmonic or Higher
l
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
l
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400μA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600μA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
(Note 8)
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
0.2
1.2
1.1
0.2
10
3.5
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
226212p
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
(Note 8)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
(Note 8)
Single-Ended Encode Mode (ENC
–
Tied to GND)
l
l
l
1.2
0
30
3.5
3.6
4
LTC2262-12
DIGITAL INPUTS AND OUTPUTS
SYMBOL PARAMETER
DIGITAL INPUTS (CS, SDI, SCK)
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
(Note 8)
V
DD
= 1.8V, SDO = 0V
SDO = 0V to 3.6V
(Note 8)
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
1.3
0.6
–10
3
200
–10
4
10
10
TYP
MAX
UNITS
V
V
μA
pF
Ω
μA
pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV
DD
= 1.8V
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OD
V
OS
R
TERM
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
I
O
= –500μA
I
O
= 500μA
I
O
= –500μA
I
O
= 500μA
I
O
= –500μA
I
O
= 500μA
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
1.750
1.790
0.010
1.488
0.010
1.185
0.010
0.050
V
V
V
V
V
V
454
1.375
mV
mV
V
V
Ω
OV
DD
= 1.5V
OV
DD
= 1.2V
DIGITAL DATA OUTPUTS (LVDS MODE)
247
1.125
350
175
1.250
1.250
100
POWER REQUIREMENTS
SYMBOL PARAMETER
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
Power Dissipation
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
CONDITIONS
(Note 10)
(Note 10)
DC Input
Sine Wave Input
Sine Wave Input, OV
DD
=1.2V
DC Input
Sine Wave Input, OV
DD
=1.2V
l
l
l
l
MIN
1.7
1.1
TYP
1.8
80.9
82.7
5.1
146
155
MAX
1.9
1.9
UNITS
V
V
mA
mA
mA
mW
mW
CMOS Output Modes: Full Data Rate and Double Data Rate
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