AND711AST-30/-EO
240 x 64 Dots
Intelligent Graphic Display
The AND711AST-30/-EO is a full dot matrix LCD module
including an LCD controller and display RAM. This device
can display graphic patterns and symbols and is suitable for
a message display for various instruments such as business
machine terminals.
Features
•
•
•
•
•
•
•
•
•
•
•
• RoHS Compliant
Absolute Maximum Ratings
Item
Supply Voltage
EL Drive Voltage
(f
EL
= 1 kHz)
Input Voltage
Operating Temperature
Storage Temperature
EL Driving Freq. (EO)
Symbol
V
DD
V
EE
V
EL
V
IN
T
op
T
stg
f
EL
Rating
5.5
-19
130
–.3
≤
V
IN
≤
+.3
0 to +50
-20 to +70
1
Unit
V
V
rms
V
°C
˚C
kHz
Super twist
40 character x 8 line capability
Excellent readability and high contrast ratio
8-bit parallel bus for read/write data by CPU interface
Built-in LCD controller and display RAM (8k byte)
Character mode, graphic mode, and character and graphic
combination mode
RoHS compliant
Wide operating temperatures range (0°C to + 50°C)
Compact and easily mounted on any equipment
User-selectable font–6 x 8 or 8 x 8
Available with EL backlighting attached (-EO option)
Dot Matrix Dimensions
Electrical Characteristics (TA = 25°C)
Item
Supply Voltage
High Level In Voltage
(V
DD
= 5.0V)
Low Level In Voltage
(V
DD
= 5.0V)
Mechanical Characteristics
Item
Outline
Dimensions
Number of Dots
# of Characters
Viewing Area
Bezel Opening
Dot Size
Dot Pitch
Weight (approx.)
Specification
180 (W) x 65 (H) x 10 (D)
240 (W) x 64 (H)
40 x 8 (320) Characters
6 x 8 dot format, alpha-numeric
132 (W) x 39 (H)
132 (W) x 39 (H)
0.49 (W) x 0.49 (H)
0.53 (W) x 0.53 (H)
I20/150 (ST/EO)
mm
mm
mm
mm
gram
Product specifications contained herein may be changed
without prior notice. It is therefore advisable to contact
Purdy Electronics before proceeding with the design of
equipment incorporating this product.
7/20/07
Symbol
V
DD
V
EE
V
IN
V
IL
V
OH
V
OL
I
DD
Min.
4.5
–5.75
2.8
–
V
DD
–0.3
–
–
–
–
Typ.
5.0
–8.5
–
–
–
–
16.0
2.4
4.0
Max.
5.5
–11.5
5
Unit
V
V
0.8
–
0.3
25.0
3.0
10
V
V
mA
(2)
Unit
mm
High Level Output Volt.
(V
DD
= 5.0V)
Low Level Output Volt.
(V
DD
= 5.0V)
Power Consumption
(1)
I
EE
I
EL
1. All dots on.
(V
DD
= .5V, V
EE
= –8.5V, V
EL
=110, f
EL
= 500 Hz or at Typ.)
2. mA rms
1
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel: 408.523.8200 • Fax: 408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com
AND711AST-30/-EO
Intelligent Graphics Display
Optical Characteristics (TA = 25˚C,
φ
= 0°,
θ
= 0)
Item
Viewing Angle
Contrast
Turn On
Turn Off
Symbol
Right to Left
Up & Down
K
T
on
T
off
Min.
–
–
2.5
-
-
Typ.
80
55
4.8
200
250
Max.
–
–
-
350
300
Unit
degree
-
ms
ms
Temperature Variations
Temperature
0°C
+25°C
+50°C
V
DD
–V
EE
Power Supply
The LCD panel is driven by the voltage V
DD
–V
EE
, so an
adjustable V
EE
is required for contrast control and
temperature compensation.
13.9
12.5
10.8
Note: Refer to Applications Section for definitions of viewing
angle, contrast ratio, response time (on and off) and
luminance.
Connector Pin Assignment
Pin No.
1
2
3
4
5
6
7
Signal
FGND
GND
V
DD
V
EE
WR
RD
CE
Function
Frame Ground (connected to metal bezel)
Ground (signal)
Power Supply for logic (5V)
Power Supply for LCD Drive (–8.5 ±3V)
Data Write
Data Read
Chip Enable
WR = “L”, C/D = “H”: Command Write
WR = “L”, C/D = “L”: Data Write
RD = “L”, C/D = “H”: Status Read
RD = “L”, C/D = “L”: Data Read
No connection
Controller Reset (Active Pullup Required)
Data Input/Output
Data Input/Output
Data Input/Output
Data Input/Output
Data Input/Output
Data Input/Output
Data Input/Output
Data Input/Output
Font select. Open or connect to V
DD
: 6 x 8 dot
Connect to ground: 8 x 8 dot
No connection
C/D
R2
Example of Variable Negative Voltage Supply
V
DD
GND
R1
T
R
V
EE
LCD Module
R1 = 10k, R2 = 10k, T
R
2SA1102 or equivalent
Timing Relationships and Diagram
Signal Timing Relationships
Item
C/D Set Up Time
C/D Hold Time
CE
,
RD
,
WR
8
C/D
Symbol
t
CDS
t
CDH
t
CE,
t
RD,
t
WR
t
DS
t
DH
t
ACC
t
OH
Min.
100
10
80
80
40
–
10
Max.
–
–
–
–
–
150
50
Unit
9
10
11
12
13
14
15
16
17
18
19
20
NC
RESET
D0
D1
D2
D3
D4
D5
D6
D7
FS
NC
Pulse Width
Data Set Up Time
Data Hold Time
Access Time
Output Hold Time
Timing Diagram
ns
t
CDS
CE
t
CP
,t
RD
,t
WP
RD, WR
t
DS
D0-D7
(WRITE)
D0-D7
(READ)
t
ACC
t
CDH
t
DH
t
OH
7/20/07
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel: 408.523.8200 • Fax: 408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com
2
AND711AST-30/-EO
Intelligent Graphics Display
Block Diagram
Because signal lines are directly connected
to C-MOS and are not pull-up or pull-down
internally, except RESET which is pull-up to
V
DD
, you must guard all signals from
external noise.
8
D0-D7
WR
RD
CE
C/D
RESET
HSCP
FR
LP
CDATA
T6963C
D0-D7
13
AD0-AD12
R/W
CE
ED
I/O0-I/O7
A0-A12
RAM
(8K byte)
X-Driver
X-Driver
X-Driver
Control Lines
80
80
80
64
Y-Driver
LCD Panel
240 x 64 Dots
V
EL
V
EL
EL Backlight
Dimensional Outline
3
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel: 408.523.8200 • Fax: 408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com
7/20/07
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
