N-Channel Enhancement Mode Field Effect Transistor
FEATURES
Type
CEP730G
CEB730G
CEF730G
V
DSS
400V
400V
400V
R
DS(ON)
1Ω
1Ω
1Ω
I
D
5.5A
5.5A
5.5A
e
@V
GS
10V
10V
10V
CEP730G/CEB730G
CEF730G
PRELIMINARY
Super high dense cell design for extremely low R
DS(ON)
.
High power and current handing capability.
Lead free product is acquired.
D
D
G
S
CEB SERIES
TO-263(DD-PAK)
G
G
D
S
G
CEP SERIES
TO-220
D
S
CEF SERIES
TO-220F
S
ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed
a
Maximum Power Dissipation @ T
C
= 25 C
- Derate above 25 C
Operating and Store Temperature Range
Tc = 25 C unless otherwise noted
Limit
Symbol
TO-220/263
V
DS
V
GS
I
D
I
DM
f
P
D
T
J
,T
stg
5.5
22
83
0.66
400
TO-220F
Units
V
V
±
30
5.5
41
0.32
-55 to 150
e
A
A
W
W/ C
C
22
e
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
R
θJC
R
θJA
1.5
62.5
Limit
2.5
65
Units
C/W
C/W
This is preliminary information on a new product in development now .
Details are subject to change without notice .
1
Rev 1. 2009.Nov.
http://www.cetsemi.com
CEP730G/CEB730G
CEF730G
Electrical Characteristics
Parameter
Off Characteristics
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage Current, Forward
Gate Body Leakage Current, Reverse
On Characteristics
Static Drain-Source
On-Resistance
Forward Transconductance
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
b
c
c
b
Tc = 25 C unless otherwise noted
Symbol
BV
DSS
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
I
S
f
V
SD
V
GS
= 0V, I
S
= 3A
V
DS
= 320V, I
D
=3.5A,
V
GS
= 10V
Test Condition
V
GS
= 0V, I
D
= 250µA
V
DS
= 400V, V
GS
= 0V
V
GS
= 30V, V
DS
= 0V
V
GS
= -30V, V
DS
= 0V
V
GS
= V
DS
, I
D
= 250µA
V
GS
= 10V, I
D
= 3A
V
DS
= 50V, I
D
= 5A
2
0.8
6
590
105
20
15
7
30
5
14
2.5
6
5.5
1.5
30
14
60
10
18
Min
400
10
100
-100
4
1
Typ
Max
Units
V
µA
nA
nA
V
Ω
S
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
A
V
Gate Threshold Voltage
V
DS
= 25V, V
GS
= 0V,
f = 1.0 MHz
V
DD
= 200V, I
D
= 3.5A,
V
GS
= 10V, R
GEN
=12Ω
Drain-Source Diode Characteristics and Maximun Ratings
Notes :
a.Repetitive Rating : Pulse width limited by maximum junction temperature .
b.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2% .
c.Guaranteed by design, not subject to production testing.
d.Limited only by maximum temperature allowed .
e.Pulse width limited by safe operating area .
f.Full package I
S(max)
= 5A .
2
CEP730G/CEB730G
CEF730G
6
5
4
3
2
1
0
V
GS
=10,8,7,6V
12
10
8
6
4
25 C
2
0
T
J
=125C
-55 C
4
5
6
I
D
, Drain Current (A)
V
GS
=4V
0
1
2
3
4
5
6
I
D
, Drain Current (A)
1
2
3
V
DS
, Drain-to-Source Voltage (V)
Figure 1. Output Characteristics
900
750
600
450
300
150
0
Coss
Crss
0
5
10
15
20
25
Ciss
2.6
2.2
1.8
1.4
1.0
0.6
0.2
-100
V
GS
, Gate-to-Source Voltage (V)
Figure 2. Transfer Characteristics
I
D
=3A
V
GS
=10V
R
DS(ON),
Normalized
R
DS(ON)
, On-Resistance(Ohms)
C, Capacitance (pF)
-50
0
50
100
150
200
V
DS
, Drain-to-Source Voltage (V)
Figure 3. Capacitance
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
-50
V
DS
=V
GS
T
J
, Junction Temperature( C)
Figure 4. On-Resistance Variation
with Temperature
I
S
, Source-drain current (A)
V
GS
=0V
10
1
V
TH
, Normalized
Gate-Source Threshold Voltage
I
D
=250µA
10
0
10
-25
0
25
50
75
100
125
150
-1
0.4
0.6
0.8
1.0
1.2
1.4
T
J
, Junction Temperature( C)
Figure 5. Gate Threshold Variation
with Temperature
V
SD
, Body Diode Forward Voltage (V)
Figure 6. Body Diode Forward Voltage
Variation with Source Current
3
CEP730G/CEB730G
CEF730G
V
GS
, Gate to Source Voltage (V)
10
8
6
4
2
0
V
DS
=320V
I
D
=3.5A
10
2
R
DS(ON)
Limit
I
D
, Drain Current (A)
10
1
100ms
1ms
10ms
DC
10
0
0
4
8
12
16
10
-1
T
C
=25 C
T
J
=150 C
Single Pulse
10
0
10
1
10
2
10
3
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
V
DD
t
on
V
IN
V
GS
R
GEN
G
R
L
D
V
OUT
t
d(on)
V
OUT
10%
V
DS
, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
t
off
t
r
90%
t
d(off)
90%
10%
t
f
INVERTED
90%
S
V
IN
50%
10%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
10
0
r(t),Normalized Effective
Transient Thermal Impedance
D=0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
10
-1
10
-2
Single Pulse
10
-3
-2
1. R
θJC
(t)=r (t) * R
θJC
2. R
θJC
=See Datasheet
3. T
JM-
T
C
= P* R
θJC
(t)
4. Duty Cycle, D=t1/t2
10
10
-1
10
0
10
1
10
2
10
3
10
4
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
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