W191
Skew Controlled SDRAM Buffer
Features
• Six skew controlled CMOS outputs
• Output skew between any two outputs is less than 150 ps
• SMBus Serial configuration interface
• 2.5 ns to 5 ns propagation delay
• DC to 133 MHz operation (Commercial)
• DC to 100 MHz operation (Industrial)
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 16-pin SSOP
(Small Shrink Outline Package)
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V ±5%
Operating Temperature: (Commercial) ............. 0°C to +70°C
Operating Temperature: (Industrial) .............. –40°C to +85°C
Input Threshold:...................................................1.5V typical
Maximum Input Voltage: .................................. V
DDQ3
+ 0.5V
Input Frequency: (Commercial) ........................0 to 133 MHz
Input Frequency: (Industrial).............................0 to 100 MHz
BUF_IN to SDRAM0:5 Propagation Delay:.......2.5 ns to 5 ns
Min. Output Edge Rate: ............................................. 1.0V/ns
Max. Output Skew: ..................................................... 150 ps
Output Duty Cycle:...................................45/55% worst case
Output Impedance: ...................................................15 typ.
Block Diagram
Pin Configuration
[1]
SDRAM0
GND
SDRAM0
SDRAM1
SDRAM2
SDATA
SCLOCK
SMBus
Device Control
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDQ3
SDRAM5
GND
SDRAM4
VDDQ3
SDRAM3
GND
SCLK
SDRAM1
BUF_IN
GND
SDRAM2
VDDQ3
SDATA
BUF_IN
SDRAM3
SDRAM4
SDRAM5
Note:
1. Internal pull-up resistor of 250K on SDATA and SCLK.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 9
www.SpectraLinear.com
W191
Pin Definitions
Pin Name
SDRAM0:5
Pin No.
1, 3, 6,
11, 13, 15
4
8
9
7, 12, 16
2, 5, 10,
14
Pin
Type
O
Pin Description
SDRAM Outputs:
Provides buffered copy of BUF_IN. The propagation delay from a
rising input edge to a rising output edge is 2.5 to 5 ns. All outputs are skew controlled
to within ±150 ps of each other.
Clock Input:
This clock input has an input threshold voltage of 1.5V (typ).
SMBus Data input:
Data should be presented to this input as described in the SMBus
section of this data sheet. Internal 250-k pull-up resistor.
SMBus clock input:
The SMBus Data clock should be presented to this input as
described in the SMBus section of this data sheet. Internal 250-k pull-up resistor.
Power Connection:
Power supply for core logic and output buffers. Connected to
3.3V supply.
Ground Connection:
Connect all ground pins to the common system ground plane.
Serial Control
Serial control data is written to the W191 in ten bytes of eight
bits each. Bytes are written in the order shown in
Table 1
Writing Data Bytes
Each bit in the data bytes control a particular device function.
Bits are written MSB (most significant bit) first, which is bit 7.
Table 1
gives the bit formats for registers located in Data
Bytes 0-2.
BUF_IN
SDATA
SCLOCK
VDDQ3
GND
I
I/O
I
P
G
Overview
The W191 is a skew controlled fanout buffer optimized for
interface with registered DIMMs.
Functional Description
Output Drivers
The W191 output buffers are CMOS type which deliver a
rail-to-rail (GND to VDD) output voltage swing into a nominal
capacitive load. Thus, output signaling is both TTL and CMOS
level compatible. Nominal output buffer impedance is 15 .
Table 1. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W191 to accept the bits in Data Bytes 0-6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W191 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W191, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W191, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
The data bits in these bytes set internal W191 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to
Table 2.
2
Command Code
Don’t Care
3
Byte Count
Don’t Care
4
5
6
7
8
9
10
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to
Table 2
Don’t Care
Rev 1.0, November 20, 2006
Page 2 of 9
W191
Table 2. Data Bytes 0–2 Serial Configuration Map
[2]
Affected Pin
Bit(s)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Pin No.
6
--
--
--
--
3
--
1
--
15
--
--
13
--
--
--
11
--
--
--
--
--
--
--
Pin Name
SDRAM2
--
--
--
--
SDRAM1
--
SDRAM0
--
SDRAM5
--
--
SDRAM4
--
--
--
SDRAM3
--
--
--
--
--
--
--
Control Function
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
Low
--
--
--
--
Low
--
--
--
Low
--
--
Low
--
--
--
Low
--
--
--
--
--
--
--
Data Byte 0 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Active
--
--
--
--
Active
--
--
--
Active
--
--
Active
--
--
--
Active
--
--
--
--
--
--
--
Bit Control
1
Data Byte 1 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Data Byte 2 SDRAM Active/Inactive Register (1 = Enable, 0 = Disable)
Note:
2. At power up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
Rev 1.0, November 20, 2006
Page 3 of 9
W191
Absolute Maximum Ratings
[3]
Stresses greater than those listed in this table may cause
permanent damage to the device. These represent a stress
Parameter
V
DDQ3
, V
IN
T
STG
T
B
T
A
T
A
Description
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature under Bias
Operating Temperature (Commercial)
Operating Temperature (Industrial)
rating only. Operation of the device at these or any other condi-
tions above those specified in the operating sections of this
specification is not implied. Maximum conditions for extended
periods may affect reliability.
Rating
–0.5 to + 7.0
–65 to + 150
–55 to + 125
0 to + 70
–40 to + 85
Unit
V
°C
°C
°C
°C
V
DDQ3
= 3.3V ± 5%
[4]
Parame-
ter
I
DD
I
DD
DC Electrical Characteristics:
T
A
= 0°C to +70°C (Commercial), V
DDQ3
= 3.3V ± 5%,T
A
= –40°C to +85°C (Industrial),
Description
3.3V Supply Current
3.3V Supply Current in three-state
Test Condition
BUF_IN = 100 MHz
BUF_IN = 100 MHz
Min.
Typ.
173
5
Max.
Unit
mA
mA
Logic Inputs (BUF_IN, OE, SCLOCK, SDATA)
V
IL
V
IH
I
ILEAK
I
ILEAK
Input Low Voltage
Input High Voltage
Input Leakage Current, BUF_IN
Input Leakage Current
[5]
GND–0.3
2.0
–5
–20
0.8
V
DDQ3
+0.5
+5
+5
V
V
µA
µA
Logic Outputs (SDRAM0:5)
V
OL
V
OH
I
OL
I
OH
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
I
OL
= 1 mA
I
OH
= –1 mA
V
OL
= 1.5V
V
OH
= 1.5V
3.1
65
70
100
110
160
185
50
mV
V
mA
mA
Pin Capacitance/Inductance
C
IN
C
OUT
L
IN
Input Pin Capacitance (Except BUF_IN)
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
Notes:
3. Multiple supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
transmission lines with 20 pF capacitors.
4. Outputs loaded by 6” 60
5. OE, SCLOCK, and SDATA logic pins have a 250-k internal pull-up resistor (not CMOS level).
Rev 1.0, November 20, 2006
Page 4 of 9
W191
AC Electrical Characteristics:
T
A
= 0°C to +70°C (Commercial), V
DDQ3
= 3.3V ± 5%,T
A
= -40°C to +85°C (Industrial),
V
DDQ3
= 3.3V ± 5% (Lump Capacitance Test Load = 30pF)
Parameter
f
IN
f
IN
t
R
t
F
t
SR
t
SF
t
EN
t
DIS
t
PR
t
PF
t
D
Z
o
Description
Input Frequency (Commercial)
Input Frequency (Industrial)
Output Rise Edge Rate
Output Fall Edge Rate
Output Skew, Rising Edges
Output Skew, Falling Edges
Output Enable Time
Output Disable Time
Rising Edge Propagation Delay
Falling Edge Propagation Delay
Duty Cycle
AC Output Impedance
Measured at 1.5V
1.0
1.0
2.5
2.5
45
15
Measured from 0.4V
to 2.4V
Measured from 2.4V
to 0.4V
Test Condition
Min.
0
0
1.0
1.0
Typ.
Max.
133
100
4.0
4.0
150
150
8.0
8.0
5.0
5.0
55
Unit
MHz
MHz
V/ns
V/ns
ps
ps
ns
ns
ns
ns
%
Rev 1.0, November 20, 2006
Page 5 of 9
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