DA9081.006
1 August, 2005
MAS9081
•
Dual Band Receiver IC
•
High Sensitivity
•
Very Low Power Consumption
•
Wide Supply Voltage Range
•
Power Down Control
•
Control for AGC On
•
High Selectivity by Crystal Filter
•
Fast Startup Feature
DESCRIPTION
The MAS9081 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to
receive time signals in the frequency range from 40
kHz to 100 kHz. Only a few external components are
required for time signal receiving. The circuit has
preamplifier, wide range automatic gain control,
demodulator and output comparator built in. The
output signal can be processed directly by an
additional digital circuitry to extract the data from the
received signal. The control for AGC (automatic gain
control) can be used to switch AGC on or off if
necessary. MAS9081 supports dual band operation
by switching between two crystal filters and an
additional antenna tuning capacitor.
MAS9081 has differential input and different internal
compensation capacitor options for compensating
shunt capacitances of different crystals (See ordering
information on page 12).
FEATURES
•
•
•
•
•
•
•
•
•
•
Dual Band Receiver IC
Highly Sensitive AM Receiver, 0.4
µV
RMS
typ.
Wide Supply Voltage Range from 1.1 V to 5 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
APPLICATIONS
•
Dual Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HGB
(Switzerland) and BPC (China)
BLOCK DIAGRAM
QO2
RFIP
RFIM
AGC Amplifier
Demodulator
&
Comparator
OUT
QO1
QI
AON
RFI2
Power Supply/Biasing
VDD
VSS PDN1 PDN2
AGC
DEC
1 (12)
DA9081.006
1 August, 2005
MAS9081 PAD LAYOUT
9081Ax,
x=1, 3, 4 or 5
VDD
QO2
QO1
QI
AGC
PDN2
OUT
VSS
RFI2
RFIM
RFIP
PDN1
AON
DEC
1494
µ
m
DIE size = 1.49 x 1.69 mm; PAD size = 80 x 80
µm
Note:
Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or
left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component
assembly are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
Quartz Filter Input for Crystals
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
Positive Receiver Input
Negative Receiver Input
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
Name
VDD
QO2
QO1
QI
AGC
PDN2
OUT
DEC
AON
PDN1
RFIP
RFIM
RFI2
VSS
X-coordinate
174
µm
174
µm
174
µm
174
µm
174
µm
174
µm
175
µm
1318
µm
1318
µm
1318
µm
1318
µm
1318
µm
1318
µm
1318
µm
Y-coordinate
1452
µm
1247
µm
1043
µm
839
µm
633
µm
430
µm
224
µm
240
µm
444
µm
648
µm
853
µm
1057
µm
1262
µm
1466
µm
Note
1688
µ
m
3
1
2
3
4
4
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
-
Internal pull-up with current < 1
µA
which is switched off at power down
3) PDN1 = VDD and PDN2 = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down controlled to power up
4) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistances against ground
2 (12)
DA9081.006
1 August, 2005
FREQUENCY SELECTION
The frequency selection and power down control is
accomplished via two digital control pins PDN1 and
PDN2. The control logic is presented in table 1.
Table 1
Frequency selection and power down control
PDN1
PDN2
RFI2 Switch
Selected Crystal
Output
High
High
Low
Low
High
Low
High
Low
Open
Open
Closed
Closed
-
QO1
QO2
QO2
Description
Power down
Frequency 1
Frequency 2, RFI2 capacitor connected in
parallel with antenna
Frequency 2, RFI2 capacitor connected in
parallel with antenna
If frequency 2 is selected then RFI2 switch is closed
to connect C
ANT2
in parallel with ferrite antenna and
tune it to frequency 2. Then only crystal output QO2
is active. Frequency 2 is lower frequency of the two
selected frequencies.
It is recommended to switch the device to power
down for 50ms before switching to another
frequency. This guarantees fast startup in switching
to another frequency. The 50ms power down period
is used to discharge AGC capacitor and to initialize
fast startup conditions.
The internal antenna tuning capacitor switch (RFI2)
and crystal filter output switches (QO1, QO2) are
controlled according table 1. See switch in block
diagram on page 1.
If frequency 1 is selected the RFI2 switch is open
and only crystal output QO1 is active. Antenna
frequency is determined by antenna inductor L
ANT
(see Typical Application on page 5), antenna
capacitor C
ANT1
and parasitic capacitances related
to antenna inputs RFI1, RFI2 and RFI3 (see
Antenna Tuning Considerations below). Frequency
1 is the higher frequency of two selected
frequencies.
ANTENNA TUNING CONSIDERATIONS
The ferrite bar antenna having inductance L
ANT
and
parasitic coil capacitance C
COIL
is tuned to two
reception frequencies f
1
and f
2
by parallel capacitors
C
ANT1
and C
ANT2
. The receiver input stage and
internal antenna capacitor switch have capacitances
(C
RFI1
, C
OFF2
) which affect the resonance
Frequency f
1
(higher frequency):
C
TOT1
=C
COIL
+C
ANT1
+C
RFI1
+C
OFF2
=C
COIL
+C
ANT1
+6.5pF+37pF=C
COIL
+C
ANT1
+ 43.5pF,
f
1
=
Frequency f
2
(lower frequency):
C
TOT2
=C
COIL
+C
ANT1
+C
ANT2
+C
RFI1
=C
COIL
+C
ANT1
+C
ANT2
+ 6.5pF,
f
2
=
frequencies. C
OFF2
is switch capacitance when
switch is open. When the switch is closed this
capacitance is shorted by on resistance of the
switch and is effectively eliminated. Following
relationships can be written into two tuning
frequencies.
1
2
π
L
ANT
⋅
C
TOT
1
1
2
π
L
ANT
⋅
C
TOT
2
3 (12)
DA9081.006
1 August, 2005
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
V
DD
-V
SS
V
IN
P
MAX
T
OP
T
ST
Conditions
Min
-0.3
V
SS
-0.3
-40
-55
Max
6
V
DD
+0.3
100
+85
+150
Unit
V
V
mW
o
C
o
C
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25°
C
Parameter
Operating Voltage
Current Consumption
Symbol
V
DD
I
DD
Conditions
VDD=1.4 V, Vin=0
µVrms
VDD=1.4 V, Vin=20 mVrms
VDD=3.6 V, Vin=0
µVrms
VDD=3.6 V, Vin=20 mVrms
Min
1.10
Typ
64
37
67
40
Max
5
Unit
V
µA
31
27
40
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
RFI2 Switch On Resistance
RFI2 Switch Off Resistance
RFI2 Switch Off
Capacitance
Input Levels |l
IN
|<0.5
µA
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
Output Pulse
I
DDoff
f
IN
V
IN min
V
IN max
R
RFI
C
RFI
R
ON2
R
OFF2
C
OFF2
V
IL
V
IH
|I
OUT
|
T
100ms
T
200ms
T
500ms
T
800ms
0.4
20
f=40kHz..77.5 kHz
VDD=1.4 V
10
37
270
6.5
3.8
91
65
0.1
100
1
µA
kHz
µVrms
mVrms
kΩ
pF
Ω
MΩ
pF
0.2 V
DD
0.8 V
DD
5
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
Fast Start-up, Vin=0.4
µVrms
Fast Start-up, Vin=20 mVrms
50
150
400
700
500
800
1.3
3.5
50
140
230
600
900
V
µA
ms
ms
ms
ms
s
Startup Time
Output Delay Time
T
Start
T
Delay
100
ms
4 (12)
DA9081.006
1 August, 2005
TYPICAL APPLICATION
Note 1
X
2
X
1
Optional
Control
for AGC on/hold
QI
AON
Demodulator
&
Comparator
OUT
Receiver
Output
QO2
RFIP
L
ANT
Ferrite
Antenna
C
ANT1
C
ANT2
RFIM
QO1
AGC Amplifier
Power Supply/Biasing
RFI2
VDD
V
BATTERY
VSS PDN1 PDN2
AGC
+
DEC
C
AGC
C
DEC
Power Down /
Fast Startup /
Frequency Selection
Note 2
Figure 1
Application circuit of dual band receiver MAS9081
X
2
40.003kHz
X
1
60.003kHz
Optional
Control
for AGC on/hold
QI
AON
Demodulator
&
Comparator
OUT
Receiver
Output
QO2
RFIP
L
ANT
4.40 mH
Ferrite
Antenna
C
ANT1
1.5 nF
C
ANT2
2.0 nF
QO1
AGC Amplifier
RFIM
RFI2
Power Supply/Biasing
VDD
VSS PDN1 PDN2
AGC
DEC
+ C
AGC
10
µ
F
Power Down /
Fast Startup /
Frequency Selection
C
DEC
47 nF
1.4 V
Figure 2
Example circuit of dual band receiver MAS9081 for MSF/WWVB/JJY frequencies
5 (12)
FPGA/CPLD
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