DA9078.003
28 January 2004
MAS9078
AM Receiver IC
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DESCRIPTION
The MAS9078 AM-Receiver chip is a highly
sensitive, simple to use AM receiver specially
intended to receive time signals in the frequency
range from 40 kHz to 100 kHz. Only a few external
components are required for time signal receiver.
The circuit has preamplifier, wide range automatic
gain control, demodulator and output comparator
built in. The output signal can be processed directly
by an additional digital circuitry to extract the data
from the received signal. The control for AGC
(automatic gain control) can be used to switch AGC
on or off if necessary. Unlike MAS1016A and
MAS1016B, MAS9078 does not require AGC control
procedure in WWVB and JJY systems.
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
FEATURES
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Highly Sensitive AM Receiver, 0.4
µV
RMS
typ.
Wide Supply Voltage Range from 1.1 V to 3.6 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Die and TSSOP-16 Package
APPLICATIONS
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Time Signal Receiver WWVB (USA), JJY (Japan),
DCF77 (Germany) and MSF (UK)
Receiver for ASK Modulated Data Signals
BLOCK DIAGRAM
QO
QI
AON (=AGC on)
RFI
AGC Amplifier
Demodulator
&
Comparator
OUT
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
1 (10)
DA9078.003
28 January 2004
PAD LAYOUT
1702 µm
VSS RFI PDN AON DEC
MAS
1778 µm
9078Bx
VDD QO
QI
AGC OUT
DIE size = 1.70 x 1.78 mm; PAD size = 100 x 100
µm
Note:
Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or
left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component
assembly are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in the center of VDD pad
Note:
The on-chip product code 9078Bx identifies internal compensation capacitance option. x has values 1, 2,
3, 4 or 5 refering to capacitance option described in the Table 2 on page 4.
Pin Description
Power Supply Voltage
Quarz Filter Output
Quarz Filter Input
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down Input
Receiver Input
Power Supply Ground
Name
VDD
QO
QI
AGC
OUT
DEC
AON
PDN
RFI
VSS
X-coordinate
0
µm
306
µm
586
µm
866
µm
1109
µm
1109
µm
866
µm
549
µm
306
µm
16
µm
Y-coordinate
0
µm
19
µm
19
µm
19
µm
19
µm
1428
µm
1428
µm
1428
µm
1428
µm
1407
µm
Note
1
2
3
Notes:
1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1
µA
which is switched off at power down
3) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
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DA9078.003
28 January 2004
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Power Dissipation
Operating Temperature
Storage Temperature
Symbol
V
DD
-V
SS
V
IN
P
MAX
T
OP
T
ST
Conditions
Min
-0.3
V
SS
-0.3
-20
-40
Max
5.0
V
DD
+0.3
100
70
120
Unit
V
V
mW
o
C
o
C
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.4V, Temperature = 25°C
Parameter
Operating Voltage
Current Consumption
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Input Levels |l
IN
|<0.5
µA
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
Output Pulse
Symbol
V
DD
I
DD
I
DDoff
f
IN
V
IN min
V
IN max
V
IL
V
IH
|I
OUT
|
T
100ms
T
200ms
T
500ms
T
800ms
Conditions
VDD=3.6 V, Vin=0
µV
VDD=1.4 V, Vin=0
µV
Min
1.10
56
Typ
76
66
Max
3.60
95
0.1
100
1
0.2 V
DD
Unit
V
µA
µA
kHz
µVrms
mVrms
V
µA
40
0.4
20
0.8 V
DD
5
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
1
µVrms ≤
V
IN
≤
20 mVrms
Fast Start-up
Without Fast Start-up
50
150
400
700
500
800
12
3
50
140
230
600
900
ms
ms
ms
ms
s
min
ms
Startup Time
Output Delay Time
T
Start
T
Delay
100
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DA9078.003
28 January 2004
TYPICAL APPLICATION
Note 1
X1
QO
Ferrite-
Antenna
RFI
AGC Amplifier
QI
AON (=AGC on)
Demodulator
&
Comparator
OUT
Receiver
output
VDD
1.4 V
Power Supply/Biasing
VSS
PDN
Note 2
C
AGC
10 uF
C
DEM
47 nF
AGC
DEC
Note 3
Power Down /
Fast Startup
Control
Note 1: Crystal
The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The
crystal shunt capacitance C
0
should be matched as well as possible with the internal shunt capacitance
compensation capacitance C
C
. MAS9078 has five compensation capacitance options. Capacitance values and
suitable crystals are described in Table 2. See also Ordering Information (p.10).
Time-Signal System
DCF77
MSF
WWVB
JJY
Table 1
Device
MAS9078B1
MAS9078B2
MAS9078B3
MAS9078B4
MAS9078B5
Table 2
Location
Antenna Frequency
Recommended Crystal Frequency
77.503 kHz
60.003 kHz
60.003 kHz
40.003 kHz and 60.003 kHz
Germany
77.5 kHz
United Kingdom
60 kHz
USA
60 kHz
Japan
40 kHz and 60 kHz
Time-Signal System Frequencies
C
C
Crystal Description
0.75 pF
For single low C
0
crystal (Nominal value)
1.25 pF
For single high C
0
crystal
1.625 pF
For two parallel low C
0
crystals (dual band receiver)
2.5 pF
For two parallel high C
0
crystals (dual band receiver)
3.875 pF
Any crystal with parallel external compensation capacitor
Compensation Capacitance Options
Note 2: AGC Capacitor
The AGC and DEC capacitors must have low leakage currents due to very small 40 nA signal currents through
the capacitors. The insulation resistance of these capacitors should be higher than 70 MΩ. Also probes with at
least 100 MΩ impedance should be used for voltage probing of AGC and DEC pins.
Note 3: Power Down / Fast Startup Control
Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if
PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered by the falling edge of PDN
signal, i.e., controlling device from power down to power up. The startup time without using the fast startup
control can be several minutes but with fast startup it is shortened typically to 12 s.
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DA9078.003
28 January 2004
SAMPLES IN SBDIL 20 PACKAGE
NC
1
VDD 2
NC 3
QO 4
NC 5
QI 6
AGC 7
OUT 8
NC
9
NC 10
MAS9078
YYWW
XXXXX.X
20 VSS
19 NC
18 RFI
17 PDN
16 AON
15 DEC
14 NC
13 NC
12 NC
11 NC
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
PIN DESCRIPTION
Pin Name
NC
VDD
NC
QO
NC
QI
AGC
OUT
NC
NC
NC
NC
NC
NC
DEC
AON
PDN
RFI
NC
VSS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Type
P
AO
AI
AO
DO
Function
Positive Power Supply
Quartz Filter Output
1
Quartz Filter Input
AGC Capacitor
Receiver Output
Note
2
AO
DI
AI
AI
G
Demodulator Capacitor
AGC On Control
Power Down Input
Receiver Input
Power Supply Ground
3
4
Notes:
1) Pin 5 between quartz crystal filter pins must be connected to VSS to eliminate DIL package leadframe
parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1
µA
which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
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