DA9279.003
13 July 2006
MAS9279
IC FOR 10.00 – 52.00 MHz VCTCXO
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DESCRIPTION
The MAS9279 is an integrated circuit well suited to
build high end VCTCXO for telecommunication.
The trimming is done through a serial bus and the
calibration information is stored in an internal
PROM. This means no rework for trimming is
needed.
To build a VCTCXO only crystal is required in
addition to MAS9279. The compensation method is
fully analog, working continuously without
generating any steps or other interference.
Fourth Order Compensation
Frequency Stability +/- 0.3
ppm
Wide Frequency Range
Very Low Phase Noise
Low Voltage
Minimum Operating
Temperature –40 °
C
Tri State CMOS Output
FEATURES
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Very small size
Minimal current consumption
Wide operating temperature range
Very low phase noise
Programmable VC-sensitivity
Minimum operating temperature –40 °
C
Oscillator frequency output f
0
/2 version
available
APPLICATIONS
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VCTCXO for high end telecommunications
systems
TCXO for high end telecommunication
systems
BLOCK DIAGRAM
DA
CLK
PV
Fourth
Term
CUB
INF
SENS
LIN
4
f(T)
5
3
8
TE1
Σ
T
Vref
TMux
TE2
f(T)
VC
CDAC1
6
4
VDD
CDAC2
OUT
VSS
X2
X1
1 (10)
DA9279.003
13 July 2006
PIN DESCRIPTION
Pin Description
Power Supply Voltage
Programming Input
Serial Bus Clock Input
Serial Bus Data Input
Temperature Output
Test Multiplexer Output
Voltage Control Input
Crystal Oscillator Output
Crystal/Varactor Oscillator Input
Power Supply Ground
Buffer Output
Symbol
VDD
PV
CLK
DA
TE1
TE2
VC
X1
X2
VSS
OUT
x-coordinate
149
561
1000
1565
2024
2016
147
1261
518
1549
1810
y-coordinate
1340
1340
1340
1340
1340
140
140
140
140
140
140
3
3
Note
Note:
Because the substrate of the die is internally connected to GND, the die has to be connected to GND or
left floating. Make sure that GND is the first pad to be bonded. Pick-and-place and all component assembly are
recommended to be performed in ESD protected area.
Note:
Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The
coordinates may vary depending on sawing width and location, however, distances between pads are accurate.
Note 3:
Valid for MAS9279A1, A3, A5 and A7. In MAS9279A2, A4, A6 and A8 TE1 and TE2 pins have been
swapped.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Pin Voltage
Power Dissipation
Storage Temperature
ESD Rating; HBM
Symbol
V
DD
- V
SS
P
MAX
T
ST
Min
-0.3
V
SS
-0.3
-55
Max
6.0
V
DD
+ 0.3
100
150
2
Unit
V
V
mW
o
C
kV
Note
1)
2)
Note 1:
Not valid for programming pin PV
Note 2:
In X1 and X2 pins maximum ESD rating is 1.5kV
RECOMMENDED OPERATION CONDITIONS
Parameter
Supply Voltage
Supply Current
Operating Temperature
Crystal Pulling Sensitivity
Crystal Pulling Sensitivity
Crystal Load Capacitance
Crystal Load Capacitance
Symbol
V
DD
I
CC
T
OP
S
S
C
L
C
L
Conditions
Vdd = 3.3 Volt
-40
24
28
Vc = 1.2V
Vc = 1.2V
Min
2.7
Typ
3.3
6.0
28
33
8
10
Max
5.5
+85
35
38
Unit
V
mA
o
C
ppm/pF
ppm/pF
pF
pF
Note
1
2
3
2
3
Note 1:
At 26MHz crystal
Note 2:
MAS9279A1, MAS9279A3, MAS9279A5, MAS9279A7
Note 3:
MAS9279A2, MAS9279A4, MAS9279A6, MAS9279A8
2 (10)
DA9279.003
13 July 2006
ELECTRICAL CHARACTERISTICS
(recommended operation conditions)
Parameter
Frequency Range
Voltage Control Range
Voltage Control Sensitivity
Voltage Control Sensitivity
Voltage Control Sensitivity
Frequency vs. Supply Voltage
Frequency vs. Load Change
Output Voltage (10 pF, VDD 2.7 V)
Output Voltage (10 pF, VDD 5.0 V)
Rise and Fall Time (10 - 50 pF)
Output Symmetry
Compensation Range ± 1.0 ppm
Compensation Range ± 0.75 ppm
Compensation Range ± 0.3 ppm
Compensation Range Linear Part
Compensation Inflection Point
Compensation Range Cubic Part
Compensation CDAC1 (4 Bit)
Compensation CDAC2 (6 Bit)
Compensation CDAC1 (4 Bit)
Compensation CDAC2 (6 Bit)
Compensation CDAC1 (4 Bit)
Compensation CDAC2 (6 Bit)
Amplitude Start up Time
Tri State Output Buffer
ON State
OFF State
Note 1:
In TCXO leave Vc floating
Note 2:
With 23 ppm/pF crystal
Note 3:
With 28 ppm/pF crystal.
Note 4:
With 33 ppm/pF crystal
Note 5:
VDD +/- 5%
Symbol
f
o
V
C
V
CSENS
V
CSENS
V
CSENS
df
o
df
o
V
out
V
out
Min
10.00
0
7.3
8.8
10.1
Typ
Max
52.00
Vdd
10.4
13.4
14.5
±0.2
±0.2
Unit
MHz
V
ppm/V
ppm/V
ppm/V
ppm
ppm
Vpp
Vpp
ns
%
Note
1)
2)
3)
4)
5)
6)
2.3
4.5
3
45-55
T
C
T
C
T
C
a1
INF
a3
C
X1
C
X2
C
X1
C
X2
C
X1
C
X2
T
START
DA
-40
-20
10
-0.4
23
95
-1.5
-21
-2.6
-26
-3.0
-32
2
85
70
50
-0.1
31
2.4
27
2.1
32
2.6
36
o
o
o
C
C
C
9)
C
2) 7)
2) 8)
3) 7)
3) 8)
4) 7)
4) 8)
ppm/K
o
ppm
2
/K
3
ppm
ppm
ppm
ppm
ppm
ppm
ms
V
0
0.55
1.6
VDD
Note 6:
R=10 kohm +/- 10%, C=10 pF +/- 10%
Note 7:
CDAC2=6.
Note 8:
CDAC1=4.
Note 9:
With LIN=255 temperature compensation is
in off mode
3 (10)
DA9279.003
13 July 2006
IC OUTLINES
VDD
PV
CLK
DA
TE1
VDD
PV
CLK
DA
TE2
1506um
MAS9279
1506um
MAS9279
VC
X2
X1
VSS
OUT
TE2
VC
X2
X1
VSS
OUT
TE1
Die map reference
2202um
Die map reference
2202um
Figure 1.
MAS9279A1, A3, A5, A7
Figure 2.
MAS9279A2, A4, A6, A8
Note 1:
MAS9279 pads are round with 80 µm diameter at opening.
Note 2:
Pin CLK can either be connected to VSS or left floating, pin PV should be connected to Ground or left
floating and pin TE1 must be left floating in VCTCXO module end-user application.
Note 3:
Die map reference is the actual left bottom corner of the sawn chip.
SAMPLES IN SB20 DIL PACKAGE
1
2
3
20
TE2
19
OUT
18
VSS
17
X1
MAS9279
YYWW
XXXXX.X
TE1
4
DA
5
CLK
6
PV
7
VDD
8
9
10
16
15
X2
14
VC
13
12
11
Top marking:
YYWW = Year, Week
XXXXX.X = Lot number
4 (10)
DA9279.003
13 July 2006
DEVICE OUTLINE CONFIGURATION
QFN10 3x3
Top View
VC
X2
X1
VSS
OUT
VDD
PV
CLK
DA
TE1
VC
X2
X1
VSS
OUT
QFN10 3x3
Top View
VDD
PV
CLK
DA
TE2
9279
AX
YWW
A = product version
X = Load / Output version 1, 3, 5, 7
Y = year
WW = week
9279
AX
YWW
A = product version
X = Load / Output version 2, 4, 6, 8
Y = year
WW = week
5 (10)
嵌入式系统
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