DA9278.004
13 July 2006
MAS9278
IC for 10.00 – 30.00 MHz VCXO
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DESCRIPTION
The MAS9278 is an integrated circuit well suited to
build VCXO for mobile communication. The crystal
offset trimming is done through a serial bus and
the calibration information is stored in an internal
PROM.
To build a VCXO only one additional component, a
crystal, is needed.
Low Power
Wide Supply Voltage Range
True Sine Wave Output
Very High Level of Integration
Integrated Varactor
Electrically Trimmable
Very Low Phase Noise
Low Cost
FEATURES
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Very small size
Minor current draw
Wide operating temperature range
Phase noise <-130 dBc/Hz at 1 kHz offset
Programmable Vc sensitivity
APPLICATIONS
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VCXO for mobile phones
VCXO for other telecommunications systems
Replacement for TCXO modules
BLOCK DIAGRAM
VC
2
OUT
MAS9278
DA
CLK
PV
VDD
Digital
5
2
VSS
X1
XO1
X2
1 (5)
DA9278.004
13 July 2006
PIN DESCRIPTION
Pin Description
Power Supply Voltage
Serial Bus Data Input
Serial Bus Clock Input
Programming Input
Voltage Control Input
Crystal Oscillator Output
Power Supply Ground
Crystal/Varactor Oscillator Input
Buffer Output
Symbol
VDD
DA
CLK
PV
VC
X1
VSS
X2
OUT
x-coordinate
177
435
201
1042
1012
374
830
817
665
y-coordinate
172
1015
1015
1015
158
158
1008
158
1015
Note:
Because the substrate of the die is internally connected to GND, the die has to be connected to GND or
left floating. Make sure that GND is the first pad to be bonded. Pick-and-place and all component assembly are
recommended to be performed in ESD protected area.
Note:
Pad coordinates are measured from the left bottom corner of the chip to the center of the pads. The
coordinates may vary depending on sawing width and location, however, distances between pads are accurate.
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Power Dissipation
Storage Temperature
Note:
Not valid for programming pin PV.
Symbol
V
DD
- V
SS
V
IN
P
MAX
T
ST
Min
-0.3
V
SS
-0.3
-55
Max
6.0
V
DD
+ 0.3
20
150
Unit
V
V
mW
o
C
Note
1)
RECOMMENDED OPERATION CONDITIONS
Parameter
Supply Voltage
Supply Current
Operating Temperature
Crystal Load Capacitance
Symbol
V
DD
I
CC
T
C
C
L
Conditions
Vcc = 2.8 Volt
-30
7.0
Min
2.7
Typ
2.8
0.85
Max
5.5
+85
Unit
V
mA
o
C
pF
2 (5)
DA9278.004
13 July 2006
ELECTRICAL CHARACTERISTICS
(recommended operation conditions)
Parameter
Frequency Range
Voltage Control Range
Voltage Control Sensitivity
Output Voltage (10kΩ // 10 pF)
Compensation CDAC1 (2 Bit)
Compensation CDAC2 (4 Bit)
Startup Time
Symbol
f
o
V
C
V
CSENS
V
out
C
X1
C
X2
T
START
Min
10.00
0
Typ
Max
30.00
Vdd
Unit
MHz
ppm/V
Vpp
Note
15..30
1.0
C10
C20
2
C10 + 4.5
C20 + 18
1)
2)
3)
pF
pF
ms
Note 1:
programmable by DN/DP switches
Note 2:
typ C10 = 4.5 pF
Note 3:
typ C20 = 12.5 pF
IC OUTLINES
CLK
DA
OUT
VSS
PV
1182 µm
MAS9278
VDD
X1
X2
VC
Die map reference
1200 µm
Note 1:
MAS9278 pads are round with 80 µm diameter at opening.
Note 2:
Pins CLK and DA can either be connected to VSS or left floating and pin PV can either be connected to
VDD or left floating in VCXO module end-user application.
Note 3:
Die map reference is the actual left bottom corner of the sawn chip.
3 (5)
DA9278.004
13 July 2006
SAMPLES IN SB20 DIL PACKAGE
1
2
3
4
MAS9278
YYWW
XXXXX.X
20
VDD
19
18
CLK
17
DA
16
OUT
15
GND
14
13
12
PV
11
X1
5
6
Top marking:
YYWW = Year, Week
XXXXX.X = Lot number
X2
7
8
9
VC
10
4 (5)
DA9278.004
13 July 2006
ORDERING INFORMATION
Product Code
MAS9278ATG1
MAS9278A
MAS9278B1TG00
Version
A
A
B
Package
EWS tested wafers 215 µm
SMD Package TBD
EWS tested wafers 215 µm
Comments
Larger range of VC sensitivity
Larger range of VC sensitivity
Smaller range of VC sensitivity
See DAE9278 page 4 for definition of versions.
Please contact Micro Analog Systems Oy for other wafer thickness options.
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy
Kamreerintie 2, P.O. Box 51
FIN-02771 Espoo, FINLAND
Tel. +358 9 80 521
Fax +358 9 805 3213
http://www.mas-oy.com
NOTICE
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits
shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no
claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and
Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or
modification.
5 (5)
FPGA/CPLD
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