DA9188.002
23 February 2005
MAS9188
12 × 8-Bit D to A Converter
3-Pin Serial Data Interface
Low Voltage Output Buffer
Replaces 12 Potentiometers
Individually Programmable
Outputs
•
Fully Operational Down to 1.2 V
•
•
•
•
DESCRIPTION
MAS9188 is 12-channel 8-bit DAC, designed
primarily for trimmer replacement. The device is
controlled by a simple 3-line input.
The DAC is selected with the four first bits in the
serial input data (SDI-pin) and the DAC output value
is set according to the last 8 bits in the serial input
data.
FEATURES
•
•
•
•
•
•
Twelve 8-Bit DACs on a Single Monolithic Chip
Voltage Level Output
TSSOP-20 Package
Single, Low +1.2 V Supply
Power-On Reset
Functionally
and
Pin
Compatible
with
AD8802/AD8804
APPLICATIONS
•
•
•
•
High Resolution Monitors
Automatic Gain Control
Trimmer Replacement
Portable and Battery-Operated Equipment
BLOCK DIAGRAM
SDI
CLK
12-bit
Shift
Register
8-bit data
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O12
O11
O10
O9
O8
O7
XCS
Address
Decoder
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O6
O5
O4
O3
O2
O1
VREFHVREFL
VDD
GND
1 (10)
DA9188.002
23 February 2005
PIN CONFIGURATION
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
1
2
3
4
20
19
18
17
VDD
XRESET
O12
O11
O10
O9
O8
O7
SDI
CLK
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
1
2
3
4
20
19
18
17
VDD
O12
O11
O10
O9
O8
O7
SDI
CLK
VREFL
MAS9188A1
YYWW
MAS9188A2
YYWW
5
6
7
8
9
10
16
15
14
13
12
11
5
6
7
8
9
10
16
15
14
13
12
11
Top view
YYWW = year, week
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MAS9188 A1
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
CLK
SDI
O7
O8
O9
O10
O11
O12
XRESET
VDD
MAS9188 A2
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
VREFL
CLK
SDI
O7
O8
O9
O10
O11
O12
VDD
Function
DAC output reference high voltage
DAC 1, address 0x0
DAC 2, address 0x1
DAC 3, address 0x2
DAC 4, address 0x3
DAC 5, address 0x4
DAC 6, address 0x5
Device analog part power-down signal (active low)
Device enable signal (rising edge loads data to DAC)
Device ground-pin
Data clock / DAC output low reference voltage
Serial input data / Data clock
DAC 7, address 0x6 / Serial input data
DAC 8, address 0x7 / DAC 7, address 0x6
DAC 9, address 0x8 / DAC 8, address 0x7
DAC 10, address 0x9 / DAC 9, address 0x8
DAC 11, address 0xA / DAC 10, address 0x9
DAC 12, address 0xB / DAC 11, address 0xA
Device Digital part reset – middle code preset pin / DAC
12, address 0xB
Device power supply pin
MAS9188 has two bonding options available:
•
•
MAS9188A1, where VREFL pin is bonded to GND pin and XRESET pin can be used
MAS9188A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used
2 (10)
DA9188.002
23 February 2005
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply (VDD to GND)
Input Voltage Range (any other pin)
Operating Temperature Range
Storage Temperature Range
Symbol
VDD
Conditions
Min
-0.3
-0.3
-40
-65
Max
6.0
VDD + 0.3
+85
+150
Unit
V
V
°C
°C
RECOMMENDED OPERATION CONDITIONS
Parameter
Supply Voltage Range
Operating Temperature Range
Symbol
VDD
Temp
Conditions
Min
1.2
-40
Typ
3.6
Max
5.5
+85
Unit
V
°C
ELECTRICAL CHARACTERISTICS
DC Parameters
◆
Digital Inputs
Parameter
DAC Resolution
DAC Differential Nonlinearity Error
DAC Integral Nonlinearity Error
DAC Full-scale Error
DAC Zero Code Error
DAC Output Resistance
◆
Reference Input
Parameter
REFH Voltage Range
REFL Voltage Range (MAS9188A2 only)
REFH Input Resistance
REFL Input Resistance
ROUT Matching (∆R
OUT
/R
OUT
)
VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C
≤
T
A
≤
+85°C unless otherwise noted
Symbol
N
DNL
INL
GFSE
BZSE
ROUT
Conditions
Min
-1
-1
-1
-1
3
Typ
8
Max
+1
+1
+1
+1
Unit
Bits
LSB
LSB
LSB
LSB
kΩ
5
8
VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C
≤
T
A
≤
+85°C unless otherwise noted
Symbol
VREFH
VREFL
RREFH
RREFL
RMATCH
Conditions
V
REFH
> V
REFL
V
REFH
> V
REFL
Min
0
0
0.5
Typ
Max
VDD
VDD
Unit
1.1
1.1
0.4
2
kΩ
kΩ
%
3 (10)
DA9188.002
23 February 2005
◆
Digital Input
Parameter
Digital Logic High
Digital Logic Low
Digital Input Current
◆
Power Supplies
Parameter
Power Supply Range
Supply Current
Shutdown Current
VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C
≤
T
A
≤
+85°C unless otherwise noted
Symbol
VIH
VIL
IIL
Conditions
Min
0.7 × VDD
Typ
Max
0.3 × VDD
±
1
Unit
µA
VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C
≤
T
A
≤
+85°C unless otherwise noted
Symbol
VDD
IDD
ISHDN
Conditions
Min
1.2
Typ
0.01
0.01
Max
5.5
5
5
Unit
V
µA
µA
AC Parameters
◆
AC Characteristics
Dynamic Performance
VDD = 2.4…5.5 V, VREFH = VDD, VREFL = 0 V, -40°C
≤
T
A
≤
+85°C unless otherwise noted
Parameter
Power Supply Sensitivity
Power Supply Sensitivity (100 Hz)
Vout Settling time (±1/2 LSB error band)
Crosstalk between adjacent outputs
Switching Characteristics
Symbol
∆V
OUT
∆V
DD
PSRR
TS
CT
Conditions
∆V
DD
= 1.1 × V
DD
–
0.9 × V
DD
Min
Typ
0.12
65
5
50
Max
Unit
%
dB
µs
dB
VDD = 3.6 V, VREFH = VDD, VREFL = 0 V, T
A
= +25°C unless otherwise noted
Parameter
Input Clock High Pulse Width
Input Clock Low Pulse Width
Data Setup Time
Data Hold Time
XCS Fall to First Clock Pulse Fall
XCS High Pulse Width
CLK Rise to XCS Rise Hold Time
XCS Rise to CLOCK Rise Setup
RESET Pulse Width
Symbol
TCH
TCL
TDS
TDH
TCLCL
TCSW
TCSH
TCS1
TRS
Conditions
Min
Typ
17
8
-7
24
18
10
22
7
18
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 (10)
DA9188.002
23 February 2005
OPERATING MODES
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)
(note: VREFL = GND in case of MAS9188A1). The XRESET pin is used for middle code preset: DAC registers
are reset and middle code will appear at the DAC output.
Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.
Rising XCS-pin reads data and 12 CLK-cycles are used as the input data (4 address bits and 8 data bits). The
last 12 bits before rising XCS are used as input data.
◆
Timing diagram
SDI
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
XCS
V
OUT
APPLICATION AND TEST CIRCUIT INFORMATION
+3.0v
DAC Register Load
20
VDD
1
VREFH
Power On/Off
MAS9188A2
8
XSHDN
O12
O11
CLK
SDI
XCS
O10
O9
O8
9
O7
O6
O5
O4
O3
19
18
17
16
15
14
7
6
5
4
3
2
Controller
Clock
Data In
Chip Select
12
13
100 nF
GND
10
O2
O1
VREFL
11
5 (10)
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