Si 5 0 1 7 - EV B
E
VALUATION
B
OARD FOR
Si5017 SiPHY™ SONET/SDH
C
L O C K A N D
D
A TA
R
E C O V E R Y
IC
Description
The Si5017 evaluation board provides a platform for
testing and characterizing Silicon Laboratories’ Si5017
SiPHY™ SONET/SDH clock and data recovery IC. The
Si5017 CDR supports OC-48, STM-16, and 2.7 Gbps
FEC rates.
All high-speed I/Os are ac coupled to ease interfacing to
industry standard test equipment.
Features
Single 3.3 V power supply
Differential I/Os ac coupled
Simple jumper configuration
Functional Block Diagram
VDD
210
Ω
Jitter
Analyzer
+
REFCLK
–
+
CLKOUT
–
Si5017
+
DATAIN
–
+
DATAOUT
–
LOS
LOL
LTR
BER_ALM
DSQLCH
RESET/CAL
CLKDSBL
Z
C
= 50
Ω
Z
C
= 50
Ω
Pattern
Analyzer
Z
C
= 50
Ω
Z
C
= 50
Ω
Scope
Pulse
Generator
Z
C
= 50
Ω
Z
C
= 50
Ω
348
Ω
Pattern
Generator
Z
C
= 50
Ω
Z
C
= 50
Ω
Test Points
Jumpers
LOS_LVL
REXT
SLICE_LVL
10 kΩ
BER_LVL
Si5017-EVB
Rev. 1.0 12/02
Copyright © 2002 by Silicon Laboratories
Si5017-EVB-DS10
Si5017-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5017 Clock and Data Recovery (CDR) device by
providing access to all of the Si5017 I/Os. Device
performance can be evaluated by following the “Test
Configuration” section. Specific performance metrics
include input sensitivity, jitter tolerance, jitter generation,
and jitter transfer.
When applied, REFCLK is used to center the frequency
of the DSPLL™ so the device can lock to the data.
Ideally, the REFCLK frequency should be 1/128th,
1/32nd, or 1/16th the VCO frequency and must have a
frequency accuracy of ±100 ppm. Internally, the CDR
automatically recognizes the REFCLK frequency within
one of these three frequency ranges. Typical REFCLK
frequencies are given in Table 1. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board.
Power Supply
The evaluation board requires one 3.3 V supply. Supply
filtering is placed on the board to filter typical system
noise components; however, initial performance testing
should use a linear supply capable of supplying the
nominal voltage ±5% dc.
CAUTION:
The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 3.3 V relative to chassis
GND.
Table 1. Typical REFCLK Frequencies
SONET/SDH
SONET/SDH
with
15/14 FEC
19.44 MHz
77.76 MHz
155.52 MHz
20.83 MHz
83.31 MHz
166.63 MHz
Ratio of
VCO to
REFCLK
128
32
16
Device Powerdown
The CDR can be powered down via the RESET/CAL
signal. When asserted, the evaluation board draws
minimal current. RESET/CAL is controlled via one
jumper located in the lower left-hand corner of the
evaluation board. RESET/CAL is wired to the signal
post adjacent to the VDD post. For a valid reset to occur
when using external reference clock mode, a proper
external reference clock frequency must be applied as
specified in Table 1. CLKOUT, DATAOUT, DATAIN
CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os)
are wired to the board perimeter on 30 mil (0.030 inch)
50
Ω
microstrip lines to the end-launch SMA jacks as
labeled on the PCB. These I/Os are ac coupled to
simplify direct connection to a wide array of standard
test hardware. Because each of these signals are
differential, both the positive (+) and negative (–)
terminals must be terminated to 50
Ω.
Terminating only
one side will adversely degrade the performance of the
CDR. The inputs are terminated on the die with 50
Ω
resistors.
Note:
The 50
Ω
termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50
Ω
+ 50
Ω
= 100
Ω.
Loss-of-Lock (LOL)
Loss-of-lock (LOL) is an indicator of the relative
frequency between the data and the REFCLK. LOL
asserts when the frequency difference is greater than
±600 ppm. To prevent LOL from de-asserting
prematurely, there is hysterisis in returning from the out-
of-lock condition. LOL will be de-asserted when the
frequency difference is less than ±300 ppm.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Loss-of-Signal Alarm Threshold Control
The loss-of-signal alarm (LOS) is used to signal low
incoming data amplitude levels. The programmable
threshold control is set by applying a dc voltage level
from a low noise voltage source to the LOS_LVL pin.
The LOS_LVL is controllable through the BNC jack J10.
The mapping of the LOS_LVL voltage to input signal
alarm threshold level is shown in Figure 1. The LOS
Threshold to LOS Level is mapped as follows:
V
LOS_LVL
–
1.5
V
LOS
= ---------------------------------------
25
If this function is not used, install jumper to JP1 header.
REFCLK
REFCLK is optional for clock and data recovery within
the Si5017 device. If REFCLK is not used, jumper both
JP15 and JP16. These jumpers pull the REFCLK+ input
to VDD and REFCLK– input to GND, which configures
the device to operate without an external reference.
2
Rev. 1.0
Si5017-EVB
40 mV
LOS Threshold (mV
PP
)
30 mV
LOS Disabled
level is set by applying a dc voltage to the BER_LVL pin.
BER_LVL is controllable through the BNC jack J12.
Jumper JP7 to disable the BER alarm. Refer to the
“BER Detection” section of the Si5016/Si5017 data
sheet for threshold level programming.
LOS
Undefined
Test Configuration
40 mV/V
15 mV
0 mV
0V
1.00 V
1.50 V
1.875 V
2.25 V
2.5 V
The three critical jitter tests typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
generation. By connecting the Si5017 Evaluation Board
as shown in Figure 2, all three measurements can be
easily made.
When applied, REFCLK should be within ±100 ppm of
the frequency selected from Table 1 and RESET/CAL
must be unjumpered.
Jitter Tolerance:
Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a modulation source, a jitter
analyzer, a pattern analyzer, and a pulse generator (all
unconnected high-speed outputs must be terminated to
50
Ω).
During this test, the Jitter Analyzer directs the
Modulation Source to apply prescribed amounts of jitter
to the synthesizer source. This “jitters” the pattern
generator timebase which drives the DATAIN ports of
the CDR. The Bit-Error-Rate (BER) is monitored on the
Pattern Analyzer. The modulation (jitter) frequency and
amplitude is recorded when the BER approaches a
specified threshold. The Si5017 limiting amplifier can
also be examined during this test. Simply lower the
amplitude of the incoming data to the minimum value
typically expected at the limiting amplifier inputs
(typically 10 mV
PP
for the Si5017 device).
Jitter Generation:
Referring to Figure 2, this test
requires a pattern generator, a clock source
(synthesizer signal source), a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test, there is no
modulation of the Data Clock, so the data that is sent to
the CDR is jitter free. The Jitter Analyzer measures the
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer:
Referring to Figure 2, this test requires
a pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test, the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
LOS_LVL (V)
Figure 1. LOS_LVL Mapping
Extended LOS Hysteresis Option
An optional LOS Hysteresis Extension circuit is included
on the Si5017-EVB to provide a convenient means of
increasing the amount of LOS Alarm hysteresis when
testing and evaluating the Si5017 LOS functionality.
This simple network will extend the LOS hysteresis to
approximately 6 dB, thereby preventing unnecessary
switching on LOS for low level DATAIN signals in the
range of 20 mV
PPD
. Hysteresis is defined as the ratio of
the LOS deassert level (LOSD) and the LOS assert
level (LOSA). The hysteresis in decibels is calculated as
20log(LOSD/LOSA). This circuit is constructed with one
CMOS inverter (U2) and two resistors (R12, R13)
mounted on the underside of the PCB. If desired, this
circuit can be enabled by installing a jumper on JP17
(HYST ENABLE) located near the power entry block.
Data Slicing Level
The slicing level allows optimization of the input cross-
over point for systems where the slicing level is not at
the amplitude average. The data slicing level can be
adjusted from the nominal cross-over point of the data
by applying a voltage to the SLICE_LVL pin.
SLICE_LVL is controllable through the BNC jack J11.
The SLICE_LVL to the data slicing level is mapped as
follows:
V
SLICE_LVL
–
1.5
-
V
SLICE
= -------------------------------------------
50
If this function is not used, jumper JP6.
Bit-Error-Rate Alarm Threshold
The bit-error-rate of the incoming data can be monitored
by the BER_ALM pin. When the bit-error-rate exceeds
an externally set threshold level, BER_ALM is asserted.
BER_ALM is brought to a test point located in the upper
right-hand corner of the board. The BER_ALM threshold
Rev. 1.0
3
Si5017-EVB
Pulse
Generator
Scope
DATAOUT–
Pattern
Analyzer
GPIB
3.3 V
+ –
REFCLK+
REFCLK–
+ REFCLK
– (optional)
DATAOUT
+
–
DATAOUT+
Data Clock-
DATAIN+
DATAIN–
+
DATAIN
–
+
CLKOUT
–
CLKOUT+
CLKOUT–
Si5017-EVB
Pattern
Generator
GPIB
Clock
Data Clock+
Jitter
Analyzer
GPIB
Synthesizer
Signal Source
FM
Modulation
Source
GPIB
Figure 2. Test Configuration for Jitter Tolerance, Transfer, and Generation
4
Rev. 1.0
3.3V
L1
J13
VDD
JP2
5
LOS_N
2
NC7SZ04
U2
4
JP3
JP5
JP8
JP9
JP10
-------
LOL
JP11
POS1
POS2
1
2
C12
tantalum 10uF
C17
0603 0.1uF
3
R13
0603 10K
JP17
CLKDSBL
RESET/CAL
DSQLCH
-------
LTR
R9
0603 0
MKDSN 2,5/3-5,08
NO LOAD
HYSTERESIS
ENABLE
LOS_N
-------
LOS
JP12
J10
BNC
LOS_LVL
JP1
R12
VDD
0603 806
C18
0603 0.1uF
C13
----------------
BER_ALM
JP13
0603 100pF
C14
J11
BNC
SLICE_LVL
JP6
R10
0603 0
C19
0603 0.1uF
R11
0603 0
0603 100pF
C15
0603 100pF
C16
J12
BNC
BER_LVL
JP7
JP14
0603 100pF
11
14
18
21
25
BER_MON
C20
0603 0.1uF
1
2
8
10
J7
AMP 449692
C5
19
24
3
4
26
U1
VDDA
VDDB
VDDC
VDDD
VDDE
RES/VDDF
RES/VDDG
LTR
DSQLCH
RESET/CAL
CLKDSBL
R7
0603 4.99K
7
9
27
LOL
LOS
BER_ALM
Rev. 1.0
5
DIN+
J8
AMP 449692
0603 0.1uF
LOS_LVL
SLICE_LVL
BER_LVL
BER_MON
28
C4
DOUT-
AMP 449692
C6
0603 0.1uF
C3
DOUT-
DOUT+
16
17
0603 0.1uF
J3
DIN-
0603 0.1uF
VDD
JP15
R6
12
13
DIN+
DIN-
Si5017
AMP 449692
REFCLK+
J1
AMP 449692
0603 0.1uF
C8
0603 210
J4
5
6
REFCLK+
REFCLK-
TDI
REXT
CLKOUT-
CLKOUT+
22
23
DOUT+
CLKOUT-
AMP 449692
C2
J2
AMP 449692
C7
Reference Less Operation
(jumper both JP15 and JP16)
JP16
VDD
JP4
15
20
R8
0603 100
0603 0.1uF
C1
Si5017
0603 0.1uF
0603 0.1uF
J5
AMP 449692
REFCLK-
R5
0603 348
R1
0603 10k (1%)
J6
CLKOUT+
NO LOAD
Si5017-EVB
Figure 3. Si5017 Schematic
微控制器 MCU
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