The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such
information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
EDS-102938 Rev E
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
Quality Specifications
Parameter
ESD Rating
MTTF
Human Body Model, JEDEC Document - JESD22-A114-B
85
o
C Leadframe, 200
o
C Channel
Unit
V
Hours
Typical
8000
1.2 X 10
6
Pin Description
Pin #
1
2
3
4
Flange
Function
RF Input
V
D1
V
D2
RF Output
Gnd
Description
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
This is the drain voltage for the first stage. Nominally +28Vdc
This is the drain voltage for the 2
nd
stage of the amplifier module. The 2
nd
stage gate bias is temperature compensated to
maintain constant quiscent drain current over the operating temperature range. See Note 1.
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza’s web site.
Simplified Device Schematic
2 V
D1
Temperature
3 V
D2
Bias
Network
Q1
RFin
1
Compensation
Q2
RFout
4
Case Flange = Ground
Absolute Maximum Ratings
Parameters
1
st
Stage Bias Voltage (V
D1
)
2
nd
Value
35
35
+20
5:1
+200
+90
-20 to +90
-40 to +100
Unit
V
V
dBm
VSWR
ºC
ºC
ºC
ºC
Stage Bias Voltage (V
D2
)
RF Input Power
Load Impedance for Continuous Operation With-
out Damage
Output Device Channel Temperature
Base Plate Temperature: Operating with no
RF Present
Note 1:
The internal generated gate voltage is thermally compensated
to maintain constant quiescent current over the temperature
range listed in the data sheet. No compensation is provided for
gain changes with temperature. This can only be provided with
AGC external to the module.
Note 2:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the drain leads to
accommodate time-varying waveforms.
Note 3:
This module was designed to have it's leads hand
soldered to an adjacent PCB. The maximum soldering iron tip
temperature should not exceed 700° F, and the soldering iron tip
should not be in direct contact with the lead for longer than 10
seconds. Refer to app note AN054 (www.sirenza.com) for fur-
ther installation
instructions.
Operating Temperature Range
Storage Temperature Range
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-102938 Rev E
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
Typical Performance Curves
Gain, IMD, ACP, ALT1 vs. Output Power
Freq=881 MHz, Vdd=28V, T
Flange
=25
o
C, IS-95
ADJ BW=30KHz @ 750 KHz spacing
ALT1 BW=30KHz @1980 KHz spacing
IMD @ 1 MHz spacing
31
30
29
Gain (dB)
28
27
26
25
24
23
0
1
2
3
Output Power (W)
4
5
6
Two Tone Gain
IMD 1MHz Spacing
ACP
ALT1
0
-10
-20
-30
-40
-50
-60
-70
-80
ACP (dB), ALT1 (dB), IMD (dBc)
40
35
30
Efficiency (%)
25
20
15
10
5
0
0
2
4
6
8
10
12
Efficiency and Idd vs. Output Pow er and Tem perature
Test Board Schematic with module connections shown
Test Board Bill of Materials
Component
PCB
J1, J2
J3
C1, C10
C2, C20
C3, C30
C25, C26
C21, C22
C23, C24
Mounting
Screws
Description
Rogers 4350,
e
r
=3.5
Thickness=30mils
SMA, RF, Panel Mount Tab W /
Flange
MTA Post Header, 6 Pin, Rect-
angle, Polarized, Surface
Mount
Cap, 10mF, 35V, 10%, Tant,
Elect, D
Cap, 0.1mF, 100V, 10%, 1206
Cap, 1000pF, 100V, 10%, 1206
Cap, 68pF, 250V, 5%, 0603
Cap, 0.1mF, 100V, 10%, 0805
Cap, 1000pF, 100V, 10%, 0603
4-40 X 0.250”
Manufacturer
Rogers
Johnson
AMP
Kemet
Johanson
Johanson
ATC
Panasonic
AVX
Various
Test Board Layout
To receive Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture, contact applications
support at
support@sirenza.com.
Data sheet for evaluation circuit (XD010-EVAL) available from Sirenza website.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
4
http://www.sirenza.com
EDS-102938 Rev E
XD010-42S-D4F 869-894 MHz 8W Power Amp Module
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3:
Dimensions are in inches
Refer to Application note AN-060 “Installation Instructions for XD Module Series” for additional mounting info. App note availbale at at www.sirenza.com
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