stage Class A/AB amplifier module is a driver stage in many 900 MHz
applications. The power transistors are fabricated using Sirenza's latest,
high performance LDMOS process. This unit operates from a single volt-
age supply and has internal temperature compensation of the bias volt-
age to ensure stable performance over the full temperature range. It is a
drop-in, no-tune solution for medium power applications requiring high effi-
ciency, excellent linearity, and unit-to-unit repeatability. It is internally
matched to 50 ohms.
XD010-51S-D4F
XD010-51S-D4FY
Pb
RoHS Compliant
&
Green
Package
902-928 MHz Class A/AB
15W Power Amplifier Module
Functional Block Diagram
Stage 1
Stage 2
Product Features
Bias
Network
Temperature
Compensation
1
2
3
4
•
•
•
•
•
•
•
•
•
•
•
Available in RoHS compliant packaging
50
W
RF impedance
15W Output P
1dB
Single Supply Operation : Nominally 28V
High Gain: 32 dB at 915 MHz
High Efficiency: 30% at 915 MHz
Robust 8000V ESD (HBM), Class 3B
XeMOS II LDMOS FETS
Temperature Compensation
RF in
V
D1
V
D2
Case Flange = Ground
RF out
Applications
RFID
Point to Multipoint data radio systems
Key Specifications
Symbol
Frequency
P
1dB
Gain
Gain Flatness
IRL
Efficiency
Linearity
Delay
Phase Linearity
R
TH, j-l
Parameter
Frequency of Operation
Output Power at 1dB Compression, 915MHz
Gain at 10W Output Power (CW)
Peak to Peak Gain Variation at 10W (CW)
Input Return Loss 10W CW
Drain Efficiency at 10W CW
3 Order IMD at 10W PEP (Two Tone), 1MHz Spacing
Signal Delay from Pin 1 to Pin 4
Deviation from Linear Phase (Peak to Peak)
Thermal Resistance Stage 1 (Junction-to-Case)
rd
Unit
MHz
W
dB
dB
dB
%
dBc
nS
Deg
ºC/W
ºC/W
Min.
902
12.5
30
14
25
Typ.
15
32
0.7
18
30
-35
2.5
0.5
11
4
Max.
928
1.5
-30
Thermal Resistance Stage 2 (Junction-to-Case)
R
TH, j-2
Test Conditions Z
in
= Z
out
= 50Ω, V
DD
= 28.0V, I
DQ1
= 230 mA, I
DQ2
=158 mA, T
Flange
= 25ºC
1625-1675The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and
all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices
does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court,
Broomfield, CO 80021
Phone: (800) SMI-MMIC
1
http://www.sirenza.com
EDS-105061 Rev E
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
Quality Specifications
Parameter
ESD Rating
MTTF
Human Body Model, JEDEC Document - JESD22-A114-B
85
o
C Leadframe, 200
o
C Channel
Unit
V
Hours
Typical
8000
1.2 X 10
6
Pin Description
Pin #
1
2
3
4
Flange
Function
RF Input
V
D1
V
D2
RF Output
Gnd
Description
Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
This is the drain voltage for the first stage. Nominally +28Vdc
This is the drain voltage for the 2
nd
stage of the amplifier module. The 2
nd
stage gate bias is temperature compensated to
maintain constant quiscent drain current over the operating temperature range. See Note 1.
Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be
taken to protect against video transients that may damage the active devices.
Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for
optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza’s web site.
Simplified Device Schematic
2 V
D1
Temperature
3 V
D2
Bias
Network
Q1
RFin
1
Compensation
Q2
RFout
4
Case Flange = Ground
Absolute Maximum Ratings
Parameters
1
st
Stage Bias Voltage (V
D1
)
2
nd
Value
35
35
+20
5:1
+200
-20 to +90
-40 to +100
Unit
V
V
dBm
VSWR
ºC
ºC
ºC
Stage Bias Voltage (V
D2
)
RF Input Power
Load Impedance for Continuous Operation With-
out Damage
Output Device Channel Temperature
Operating Temperature Range
Storage Temperature Range
Note 1:
The internally generated gate voltage is thermally compen-
sated to maintain constant quiescent current over the temper-
ature range listed in the data sheet. No compensation is
provided for gain changes with temperature. This can only be
accomplished with AGC external to the module.
Note 2:
Internal RF decoupling is included on all bias leads. No addi-
tional bypass elements are required, however some applica-
tions may require energy storage on the drain leads to
accommodate time-varying waveforms.
Note 3:
This module was designed to have its leads hand soldered to
an adjacent PCB. The maximum soldering iron tip tempera-
ture should not exceed 700° F, and the soldering iron tip
should not be in direct contact with the lead for longer than 10
seconds. Refer to app note AN060 (www.sirenza.com) for fur-
ther installation instructions.
Operation of this device beyond any one of these limits may cause per-
manent damage. For reliable continuous operation see typical setup val-
ues specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging
and testing devices must be observed.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
2
http://www.sirenza.com
EDS-105061 Rev E
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
Typical Performance Curves
2 Tone Gain, Efficiency, Linearity and IRL vs Frequency
Vdd=28V, Pout=10W PEP, Delta F=1 MHz
50
45
40
Gain (dB), Efficiency (%)
35
30
25
20
15
10
5
0
880
890
900
910
920
930
940
Frequency (MHz)
Gain
IM3
IM7
Efficiency
IM5
IRL
-10
-15
-20
Gain (dB), Efficiency (%)
50
45
40
2 Tone Gain, Efficiency, Linearity vs Pout
Vdd=28V, Freq=915 MHz, Delta F=1 MHz
-20
-25
-30
-35
IMD (dBc)
-40
-45
-50
-55
IMD(dBc), IRL (dB)
-25
-30
-35
-40
-45
-50
-55
-60
950
35
30
25
20
15
10
5
0
0
2
4
6
8
10
12
14
16
Pout (W PEP)
Gain
IM3
IM7
Efficiency
IM5
-60
-65
-70
CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Pout=10W
40
Gain
Efficiency
IRL
35
-20
Input Return Loss (dB)
-15
32.5
32.25
CW Gain, Efficiency vs Pout
Vdd=28V, Freq=915 MHz
60
37.5
Gain (dB), Efficiency (%)
-17.5
50
32
40
Gain (dB)
Gain
Efficiency
30
32.5
-22.5
31.5
31.25
30
-25
20
31
27.5
-27.5
10
30.75
30.5
0
2
4
6
8
Pout (W)
10
12
14
16
0
25
880
890
900
910
920
930
940
Frequency (MHz)
-30
950
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
3
http://www.sirenza.com
EDS-105061 Rev E
Efficiency (%)
31.75
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
Test Board Schematic with module connections shown
Test Board Bill of Materials
Component
PCB
J1, J2
J3
C1, C10
C2, C20
C3, C30
C25, C26
C21, C22
C23, C24
Mounting
Screws
Description
Rogers 4350,
e
r
=3.5
Thickness=30mils
SMA, RF, Panel Mount Tab W /
Flange
MTA Post Header, 6 Pin, Rect-
angle, Polarized, Surface
Mount
Cap, 10mF, 35V, 10%, Tant,
Elect, D
Cap, 0.1mF, 100V, 10%, 1206
Cap, 1000pF, 100V, 10%, 1206
Cap, 68pF, 250V, 5%, 0603
Cap, 0.1mF, 100V, 10%, 0805
Cap, 1000pF, 100V, 10%, 0603
4-40 X 0.250”
Manufacturer
Rogers
Johnson
AMP
Kemet
Johanson
Johanson
ATC
Panasonic
AVX
Various
Test Board Layout
To receive Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture, contact applications sup-
port at
support@sirenza.com.
Data sheet for evaluation circuit (XD010-EVAL) available from Sirenza website.
303 S. Technology Court
Broomfield, CO 80021
Phone: (800) SMI-MMIC
4
http://www.sirenza.com
EDS-105061 Rev E
XD010-51S-D4F 902-928 MHz 15W Power Amp Module
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3:
Dimensions are in inches
Refer to Application note AN-060 “Installation Instructions for XD Module Series” for additional mounting info. App note availbale at at www.sirenza.com
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