SM5847AF
NIPPON PRECISION CIRCUITS INC.
High-fidelity Digital Audio, Multi-function Digital Filter
OVERVIEW
The SM5847AF is a 4/8-times oversampling (inter-
polation), 2-channel, linear-phase FIR, multi-func-
tion digital filter for digital audio reproduction
equipment. It features independent left and right-
channel digital deemphasis filters and soft muting
function.
The input/output interface supports input data in
16/18/20/24-bit words, and output data in
18/20/22/24-bit words in either 4-times or 8-times
oversampling selectable output mode.
The internal system clock operates at either 192fs or
256fs selectable speed (where fs is the audio sam-
pling frequency). Plus, the divide-by 1, 2, or 4
counter settings means that external clocks of 768fs/
384fs/192fs (192fs input) and 1024fs/512fs/256fs
(256fs input) are supported.
The SM5847AF operates from a single 3 to 5 V sup-
ply, and is available in 44-pin QFP packages.
FEATURES
s
s
s
s
s
s
s
Left/right-channel (2-channel processing)
4-times/8-times oversampling (interpolation)
• 8-times interpolation filter
- 3-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
3rd stage (4fs to 8fs): 17-tap
-
≤
±0.00002 dB passband ripple (0 to
0.4535fs)
-
≥
117 dB stopband attenuation (0.5465fs to
7.4535fs)
• 4-times interpolation filter
- 2-stage linear-phase FIR configuration
1st stage (fs to 2fs): 169-tap
2nd stage (2fs to 4fs): 29-tap
-
≤
±0.00002 dB passband ripple (0 to
0.4535fs)
-
≥
116 dB stopband attenuation (0.5465fs to
3.4535fs)
Digital deemphasis
• IIR filter configuration
• fs = 32kHz, 44.1kHz, 48kHz
• 2-channel independent ON/OFF control
26
×
24-bit parallel multiplier/32-bit accumulator
Overflow limiter
Soft muting
• 2-channel independent ON/OFF control
Input data format
s
s
s
s
s
s
s
s
s
• 2s complement, MSB first
• 3 selectable formats
- LR alternating, 16/18/20/24-bit serial, right-
justified data
- LR alternating, 24-bit serial, left-justified
data
- LR simultaneous, 24-bit serial, left-justified
data
Output data format
• 2s complement, MSB first, LR simultaneous
• 18/20/22/24-bit serial
• BCKO burst (NPC format)
Dither round-off processing
• Dither round-off ON/OFF selectable
25-bit internal data word length
Internal system clock
• 192fs/256fs selectable
• Maximum operating frequency
192fs mode: 37 MHz max (5 V)
20.7 MHz max (3 V)
256fs mode: 27.6 MHz max (5 V)
25 MHz max (3 V)
Jitter-free function
• Jitter-free/Sync mode selectable
Crystal oscillator circuit built-in
3 to 5 V supply
44-pin plastic QFP
CMOS process
ORDERING INFORMATION
D e vice
SM5847AF
P ackag e
44-pin QFP
NIPPON PRECISION CIRCUITS—1
SM5847AF
PIN DESCRIPTION
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
OMD
DOR
DOL
W C KO
B C KO
VSS
VSSAC
V D DAC
VDD
DG
NC
C KO
VSS
VDD
X TO
XTI
VSS
VDD
LRCI
DI/INF2N
BCKI
NC
NC
CKSLN
INF1N
IW1N/DIL
IW2N/DIR
VSS
VDD
OW1N
OW2N
SYNCN
RSTN
C K DV 1
C K DV 2
DEMPR
DEMPL
VDD
VSS
FSEL1
FSEL2
MUTEL
MUTER
DITHN
I/O
Ip
1
O
2
O
2
O
2
O
2
–
–
–
–
O
2
–
O
2
–
–
O
I
–
–
I
1
I
1
I
1
–
–
Ip
2
Ip
2
Ip
1
Ip
1
–
–
Ip
2
Ip
2
Ip
2
Ip
1
Ip
1
Ip
1
Ip
1
Ip
1
–
–
Ip
1
Ip
1
Ip
1
Ip
1
Ip
1
Output data rate (4fs/8fs) select pin
Right-channel data output
Left-channel data output
W ord clock output
Bit clock output
Ground
Ground
Supply voltage
Supply voltage
Deglitched signal output
No internal connection (must be open)
Master clock output
Ground
Supply voltage
Oscillator output
Oscillator input/master clock input
Ground
Supply voltage
Input data sample rate (fs) clock input
Data input/input format select pin 2
Bit clock input
No internal connection (must be open)
No internal connection (must be open)
Master clock frequency (192fs/256fs) select pin
Input format select pin 1
Input data word length select pin 1/left-channel data input
Input data word length select pin 2/right-channel data input
Ground
Supply voltage
Output data word length select pin 1
Output data word length select pin 2
Sync mode select pin
Reset input
Internal system clock frequency divider set pin 1
Internal system clock frequency divider set pin 2
Right-channel deemphasis ON/OFF pin
Left-channel deemphasis ON/OFF pin
Supply voltage
Ground
Deemphasis filter sample rate (fs) select pin 1
Deemphasis filter sample rate (fs) select pin 2
Left-channel mute ON/OFF pin
Right-channel mute ON/OFF pin
Output data dither ON/OFF pin
Description
1. Schmitt input, TTL level
2. TTL level
Ip = Pull-up input
NIPPON PRECISION CIRCUITS—4
SM5847AF
SPECIFICATIONS
Absolute Maximum Ratings
V
SS
= V
SSAC
= 0 V, V
DD
= V
DDAC
P arameter
Supply voltage range
1
Input voltage range
Storage temperature range
Pow er dissipation
Symbol
V
D D
, V
D D A C
V
I
T
stg
P
D
≤
70
°
C
≤
85
°
C
Condition
Rating
−
0.3 to 6.5
V
S S
−
0.3 to V
D D
+
0.3
−
55 to 125
900
mW
700
Unit
V
V
°
C
1. Supply lines for VDD and V D D A C , and ground lines for VSS and V S S A C , should be connected on the printed circuit board to prevent device break-
down due to potential difference when the pow er is applied.
Recommended Operating Conditions
V
SS
= V
SSAC
= 0 V, V
DD
= V
DDAC
P arameter
Supply voltage range
1
Operating temperature range
Symbol
V
D D
, V
D D A C
T
a
Rating
3.00 to 5.25
−
40 to 85
Unit
V
°
C
1. The minimum required operating voltage and consequent operating temperature vary with the maximum operating frequency and sampling mode
selected, as shown in the following table.
V
SS
= V
SSAC
= 0 V, V
DD
= V
DDAC
Internal system clock
Sampling frequency
fs (kHz)
Mode
1
192fs
192
256fs
108
2
192fs
256fs
192fs
96
256fs
55.2
3
192fs
256fs
25
10.6
14.2
Not guaranteed
20.7
27.6
18.5
M a x i m um operating
frequency (MHz)
37
M i n i mu m s u p p ly voltag e
V
D D
, V
D D A C
(V)
4.75 (5.0
−
5%)
Not guaranteed
3.00 (3.3
−
10%)
4.50 (5.0
−
10%)
3.00 (3.3
−
10%)
3.00 (3.3
−
10%)
3.00 (3.3
−
10%)
3.00 (3.3
−
10%)
−
40 to 85
Operating temperature
T
a
(
°
C)
−
40 to 70
Not guaranteed
1. Mode with internal frequency divider ratio set to 1 (CKDV 1 = C K DV2 = LOW).
2. 96 kHz + 12.5% variable pitch
3. 48 kHz + 15% variable pitch
NIPPON PRECISION CIRCUITS—5
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