PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
•
VCXO output for the 17MHz to 130MHz range
-
PLL500-17B: 17MHz to 36MHz
-
PLL500-27B: 27MHz to 65MHz
-
PLL500-37B: 65MHz to 130MHz
Low phase noise (-142 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
-
Standard: 8mA drive capability at TTL level.
-
High: 24mA drive capability at TTL level.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5 to 3.3V operation.
Available in 8-Pin SOIC or DIE.
PIN CONFIGURATION
XIN
OE^
VIN
GND
1
8
XOUT
DS^
VDD*
CLK
P500-x7B
2
3
4
7
6
5
•
•
•
•
•
•
•
•
•
^: Denotes internal Pull-up
DIE PAD LAYOUT
32 mil
(812,986)
8
1
XIN
XOUT
DRIVSEL^ 7
39 mil
DESCRIPTION
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc at 10kHz offset. The very low jitter (2.5
ps RMS period jitter) makes these chips ideal for
applications requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
2
OE^
VDD 6
3 VCON
4 GND
CLK 5
DIE ID:
PLL500-17B: C500A0505-05P
Y
X
PLL500-27B: C500A0505-05Q
PLL500-37B: C500A0505-05R
(0,0)
Note: ^ denotes internal pull up
FREQUENCY RANGE
PART #
PLL500-17B
PLL500-27B
PLL500-37B
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
DIE SPECIFICATIONS
Name
Value
Size
Reverse side
Pad dimensions
Thickness
39 x 32 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 1
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PIN AND PAD DESCRIPTION
Name
XIN
OE
VCON
GND
CLK
VDD
DRIVSEL
XOUT
Pin#
1
2
3
4
5
6
7
8
Die Pad Position
X (µm)
94.183
94.157
94.183
94.193
715.472
715.307
715.472
476.906
Y (µm)
768.599
605.029
331.756
140.379
203.866
455.726
626.716
888.881
Type
I
I
I
P
O
P
I
I
Description
Crystal input pin.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected low.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin.
Output drive select pin. High drive if set to ‘0’. Low drive if set
to ‘1’. Internal pull-up.
Crystal output pin. Ref clock input.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
SYMBOL
CONDITIONS
PLL500-17B
PLL500-27B
PLL500-47B
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Measured @ 1.4V
MIN.
17
27
65
TYP.
MAX.
36
65
130
UNITS
MHz
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
45
0.8
2.5
50
±50
ns
55
%
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 2
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
Power Supply Rejection
VCON pin input impedance
VCON modulation BW
PWSRR
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
ppm
kΩ
kHz
300
±150
100
5
Frequency change with
VDD varied +/- 10%
0V
≤
VCON
≤
3.3V, -3dB
-1
2000
45
+1
Note:
Preliminary Specifications still to be characterized. Parameters denoted with an asterisk (*) represent nominal characterization data and are not
production tested to any specific limits.
4. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 10,000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
MIN.
TYP.
2.5
-100
-125
-142
-150
-150
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 3
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
5. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
SYMBOL
I
DD
CONDITIONS
F
XIN
= 27MHz, 15pF output load
F
XIN
= 35MHz, 15pF output load
F
XIN
= 78MHz, 15pF output load
PLL500-17B
PLL500-27B
PLL500-37B Std drive up to
100MHz
PLL500-37B High drive
I
OH
= -8mA
I
OL
= 8mA
I
OH
= -4mA
Standard drive at TTL level
High drive at TTL level
MIN.
TYP.
2.8
4.2
7.2
MAX.
4
6
9
30
20
15
UNITS
mA
pF
pF
pF
pF
V
V
V
V
Allowable output load
capacitance
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level
Output drive current
Short Circuit Current
VCXO Control Voltage
C
L
(Output)
V
DD
V
OH
V
OL
2.25
2.4
V
DD
– 0.4
8
24
0
9.5
27
±50
10
3.63
0.4
mA
mA
V
VCON
V
DD
6. Crystal Specifications
PARAMETERS
Crystal Loading Rating (VCON = 1.65V)
Maximum Sustainable Drive Level
Operating Drive Level
Max C0 for PLL500-17B
Max C0 for PLL500-27B
Max C0 for PLL500-37B
C0/C1
ESR
SYMBOL
C
L
(xtal)
MIN.
TYP.
8.5
MAX.
200
UNITS
pF
µW
µW
pF
-
Ω
50
5
3.5
2.5
250
30
R
S
Note:
The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 4
PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PACKAGE INFORMATION
SOIC 8L
(Dimensions in mm)
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
e
b
C
L
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL500-X7B X X X X
PART NUMBER
NONE= TUBE
R=TAPE AND REEL
NONE=NORMAL PACKAGE
L=GREEN PACKAGE
PACKAGE TYPE
S=SSOP
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
Order Number
PLL500-X7BDC
PLL500-X7BSC
PLL500-X7BSC-R
PLL500-X7BSCL
PLL500-X7BSCL-R
Marking
P500-X7BDC
P500-X7BSC
P500-X7BSC
P500-X7BSCL
P500-X7BSCL
Package Option
Die (Waffle Pack)
8-Pin SOIC (Tube)
8-Pin SOIC (Tape and Reel)
8-Pin SOIC (Tube), GREEN
8-Pin SOIC (Tape and Reel) , GREEN
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 5
stm32/stm8
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