Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
FEATURES
•
•
•
•
•
•
•
•
•
•
Generates 12-output buffers from one input.
Supports VIA Pro266 DDR chipset.
Supports up to 2 DDR DIMMS.
Supports up to 400MHz DDR, SDRAMS.
One additional output for feedback.
6 differential clock distribution.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V Supply range.
Available in 28-pin SSOP.
PIN CONFIGURATION
FBOUT
GND
DDRT0
DDRC0
VDD2.5
GND
DDRT1
DDRC1
VDD2.5
BUF_IN
GND
DDRT2
DDRC2
VDD2.5
DDR0T
Note:
#: Active Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
DDRT5
DDRC5
VDD2.5
GND
DDRT4
DDRC4
VDD2.5
GND
DDRT3
DDRC3
VDD2.5
SCLK
SDATA
PLL103-07
BLOCK DIAGRAM
SDATA
SCLK
I2C
Control
DDR0C
DDR1T
DDR1C
DDR2T
DDR2C
DESCRIPTIONS
The PLL103-07 is designed as a 2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 12 outputs. These outputs can be
configured to support 2 DDR DIMMs. The PLL103-07
can be used in conjunction with the PLL202-04 or
similar clock synthesizer for the VIA Pro 266 chipset.
BUF_IN
DDR3T
DDR3C
DDR4T
DDR4C
DDR5T
DDR5C
FBOUT
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 1
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
PIN DESCRIPTIONS
Name
FBOUT
BUF_IN
DDRT[0:5]
DDRC[0:5]
VDD2.5
GND
Number
1
10
3,7,12,19,
23,27
4,8,13,18,
22,26
5,9,14,
17,21,25
6,11,20,24
Type
O
I
O
O
P
P
Feedback clock for chipset.
Reference input from chipset.
Description
“True” clocks of differential pair outputs.
“Complementary” clocks of differential pair outputs.
2.5V power supply.
Ground.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 2
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
I2C BUS CONFIGURATION SETTING
Address Assignment
Slave
Receiver/Transmitter
Data Transfer Rate
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Provides both slave write and readback functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode:
the
Command Byte
and
Byte
Count Byte must be sent by the master
but ignored by the slave, in
Read Mode:
the
Byte
Count Byte
will be
read by the master
then all other
Data Byte. Byte Count Byte
default at
power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
-
-
27, 26
23, 22
19, 18
Default
1
0
0
0
1
1
1
1
Description
Reserved
Reserved
Reserved
Reserved
Reserved
DDRT5, DDRC5
DDRT4, DDRC4
DDRT3, DDRC3
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 3
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
2. BYTE 7: Outputs Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
12, 13
-
7, 8
-
3, 4
Default
1
1
1
1
1
1
1
1
Description
Reserved
Reserved
Reserved
DDRT2, DDRC2
Reserved
DDRT1, DDRC1
Reserved
DDRT0, DDRC0
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 4
Preliminary
PLL103-07
2 DIMM DDR Fanout Buffer
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
ESD Voltage
SYMBOL
V
DD
V
I
V
O
T
S
T
A
MIN.
V
SS
-
0.5
V
SS
-
0.5
V
SS
-
0.5
-65
0
MAX.
7.0
V
DD
+
0.5
V
DD
+
0.5
150
70
2
UNITS
V
V
V
°C
°C
KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Operating Conditions
PARAMETERS
Supply Voltage
Input Capacitance
Output Capacitance
SYMBOL
V
DD2.5
C
IN
C
OUT
MIN.
2.375
MAX.
2.625
5
6
UNITS
V
pF
pF
3. Electrical Specifications
PARAMETERS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage
Output Low
Voltage
Output High
Current
Output Low
Current
Note:
TBM: To be measured
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
CONDITIONS
All Inputs except I2C
All inputs except I2C
V
IN
= V
DD
V
IN
= 0
IOL = -12mA,
IOL = 12mA,
VDD = 2.375V
VDD = 2.375V
MIN.
2.0
V
SS
-0.3
TYP.
MAX.
V
DD
+0.3
0.8
TBM
TBM
UNITS
V
V
uA
uA
V
1.7
0.6
-18
26
-32
35
V
mA
mA
VDD = 2.375V, VOUT=1V
VDD = 2.375V, VOUT=1.2V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 01/03/01 Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
