PLL103-01
Low Skew Buffers
FEATURES
•
•
•
•
•
•
•
•
•
•
Generate 18 copies of High-speed clock inputs.
Supports up to four SDRAM DIMMS synchronous
clocks.
Supports 2-wire I2C serial bus interface with
readback.
50% duty cycle with low jitter.
Less than 5ns delay.
Skew between any outputs is less than 250 ps.
Tri-state pin for testing.
Frequency up to 133 MHZ.
3.0V-3.7V Supply range.
48-pin SSOP package.
PIN CONFIGURATION
N/C
N/C
VDD
SDRAM0
SDRAM1
GND
VDD
SDRAM2
SDRAM3
GND
BUF_IN
VDD
SDRAM4
SDRAM5
GND
VDD
SDRAM6
SDRAM7
GND
VDD
SDRAM16
GND
VDD1
SDATA
1
2
3
4
5
6
7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N/C
N/C
VDD
SDRAM15
SDRAM14
GND
VDD
SDRAM13
SDRAM12
GND
OE^
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM17
GND
GND1
SCLK
PLL103-01
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BLOCK DIAGRAM
SDRAM0
SDATA
SCLK
I2C
Control
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
BUF_IN
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
OE
Note:
^: pull up
POWER GROUP
•
•
VDD: SDRAM( 0:17 )
VDD1: I2C Circuitry
GROUND GROUP
•
•
GND: SDRAM( 0:17 )
GND1: I2C Circuitry
KEY SPECIFICATIONS
•
•
•
•
BUFIN to SDRAM outputs Delay: 1 ~ 5 ns.
Output Slew:
≥1.5
V/ns.
Output Skew:
±250
ps.
Output Duty Cycle: 50%
±
5%.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/08/00 Page 1
PLL103-01
Low Skew Buffers
PIN DESCRIPTIONS
Name
SDRAM (0:3)
SDRAM (4:7)
SDRAM (8:11)
SDRAM (12:15)
SDRAM (16:17)
OE
BUF_IN
SDATA
SCLK
VDD
VDD1
GND
GND1
N/C
Number
4,5,8,9
13,14,17,18
31,32,35,36
40,41,44,45
21,28
38
11
24
25
3,7,12,16,20,2
9,33,37,42,46
23
6,10,15,19,22,
27,30,34,39,43
26
1,2,47,48
Type
O
O
O
O
O
I
I
B
I
P
P
P
P
-
SDRAM Byte0 Clock outputs.
SDRAM Byte1 Clock outputs.
SDRAM Byte2 Clock outputs.
SDRAM Byte3 Clock outputs.
SDRAM Byte4 Clock outputs.
Description
Tristates all outputs, active low. Has internal pull-up.
Input for fanout buffers SDRAM (0:17).
Serial data inputs for serial interface port.
3.3V Power supply for SDRAM buffer.
3.3V Power supply for I2C circuitry.
Ground for SDRAM buffer.
Power supply for I2C circuitry.
Pins are internally disconnected.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/08/00 Page 2
PLL103-01
Low Skew Buffers
I2C BUS CONFIGURATION SETTING
Address Assignment
Slave
Receiver/Transmitter
Data Transfer Rate
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
_
Provides both slave write and readback functionality
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode:
the
Command Byte
and
Byte
Count Byte must be sent by the master
but ignored by the slave, in
Read Mode:
the
Byte
Count Byte
will be
read by the master
then all other
Data Byte. Byte Count Byte
default at
power-up is = (0x09).
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 0: SDRAM(0:7) Clock Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
18
17
14
13
9
8
5
4
Default
1
1
1
1
1
1
1
1
Description
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
SDRAM2 (Active/Inactive)
SDRAM1 (Active/Inactive)
SDRAM0 (Active/Inactive)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/08/00 Page 3
PLL103-01
Low Skew Buffers
2. BYTE 1: SDRAM(8:15) Clock Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
45
44
41
40
36
35
32
31
Default
1
1
1
1
1
1
1
1
Description
SDRAM15 (Active/Inactive)
SDRAM14 (Active/Inactive)
SDRAM13 (Active/Inactive)
SDRAM12 (Active/Inactive)
SDRAM11 (Active/Inactive)
SDRAM10 (Active/Inactive)
SDRAM9 (Active/Inactive)
SDRAM8 (Active/Inactive)
3. BYTE 2: SDRAM(16:17) Clock Register
(1=Enable, 0=Disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
28
21
-
-
-
-
-
-
Default
1
1
1
1
1
1
1
1
Description
SDRAM17 (Active/Inactive)
SDRAM16 (Active/Inactive)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/08/00 Page 4
PLL103-01
Low Skew Buffers
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
SYMBOL
V
DD
V
I
V
O
T
S
T
A
MIN.
V
SS
-
0.5
V
SS
-
0.5
V
SS
-
0.5
-65
0
MAX.
7.0
V
DD
+
0.5
V
DD
+
0.5
150
70
UNITS
V
V
V
°C
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. AC/DC Electrical Specifications
PARAMETERS
Input High Current
Input Low Current
Input High Voltage
Input Low Voltage
Input Frequency
Input Capacitance
SYMBOL
I
IH
I
IL
I
IL
V
IH
V
IL
F
IN
C
IN
I
DD1
I
DD2
V
IN
= V
DD
CONDITIONS
MIN.
TYP.
MAX.
5
UNITS
uA
uA
uA
V
IN
=0V; with no pull-up resistors
V
IN
=0V; with 100k pull-up resistors
2
V
SS
−0.3
V
DD
=3.3V; All outputs loaded
Logic Inputs
C
L
= 0pf @ 66MHz
C
L
= 0pf @ 100MHz
C
L
= 30pf; RS= 33Ω @ 66MHz
C
L
= 30pf; RS= 33Ω @ 100MHz
Stopped, input at 0 or VDD
80
120
180
240
10
V
DD
+0.3
0.8
150
5
120
180
260
360
500
V
V
Mhz
PF
mA
mA
mA
mA
uA
Operating Supply
Current
I
DD3
I
DD4
I
DD5
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/08/00 Page 5
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