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SM8720AV

3-PLL Multi-Output Clock Generator

OVERVIEW

The SM8720AV is a clock generator IC with 3 built-in PLLs. It can simultaneously output a 27MHz master

clock and three other clocks with different frequency (CLK1OUT, CLK2OUT, CLK3OUT) derived from the

master clock. The 3 generated clocks can be independently turned ON/OFF using control pins and the fre-

quency of CLK3OUT can be switched, allowing unneeded clocks within a system to be switched OFF thereby

reducing current consumption. The master clock, supplied by high-stability crystal oscillator external input,

allows clocks to be generated with high precision and low jitter and which require no frequency adjustment,

making the SM8720AV ideal for digital still cameras and other applications which require multiple high-preci-

sion clocks.

FEATURES

I

PINOUT

(Top view)

I

2.7 to 3.3V supply voltage

21mA typ. current consumption

(V

DD

= 3.0V, all outputs with no load)

27MHz master clock (external input)

(internal PLL reference clock)

Generated clocks

• 27MHz master clock (REFOUT)

• 22.5792MHz (CLK1OUT)

(ON/OFF switching using control pin)

• 48.0000MHz (CLK2OUT)

(ON/OFF switching using control pin)

• 36/45/48.6MHz (CLK3OUT)

(ON/OFF switching using control pin, fre-

quency switching)

Output load

• 25pF (REFOUT)

• 15pF (all outputs excluding REFOUT)

Low jitter output

• 140ps typ. peak-to-peak (REFOUT)

• 220ps typ. peak-to-peak

(CLK1OUT, CLK3OUT)

• 220ps typ. peak-to-peak (CLK2OUT)

16-pin VSOP package (Pb free)

VDD1

FIN

VSS1

CLK3OUT

CLK3_ON

SEL1

CLK1_ON

VDD2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFOUT

VSS3

SEL2

CLK2_ON

VDD3

CLK2OUT

VSS2

CLK1OUT

PACKAGE DIMENSIONS

(Unit: mm)

Weight: 0.07g

I

Digital still cameras

ORDERING INFORMATION

Device

SM8720AV

Package

16-pin VSOP

0.65

4.4 0.2

6.4 0.2

APPLICATIONS

0.10 0.05

5.1 0.2

1.15 0.1

0.275typ

0.15

-

+ 0.1 5

0.0

0 to 10

0.10

+ 0.1

0.22

- 0.05

0.12

M

0.5 0.2

NIPPON PRECISION CIRCUITS INC.—1

SM8720AV

BLOCK DIAGRAM

Reference

Divider 1

FIN

CLK1_ON

Phase

Detector 1

Charge

Pump 1

LPF 1

VCO 1

CLK1OUT

(PLL1)

Loop

Divider 1

Reference

Divider 2

Phase

Detector 2

Charge

Pump 2

LPF 2

VCO 2

CLK2OUT

CLK2_ON

(PLL2)

Loop

Divider 2

SEL1

SEL2

Control

Logic

Reference

Divider 3

Phase

Detector 3

Charge

Pump 3

LPF 3

VCO 3

CLK3OUT

CLK3_ON

(PLL3)

Loop

Divider 3

REFOUT

PIN DESCRIPTION

Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Name

VDD1

FIN

VSS1

CLK3OUT

CLK3_ON

SEL1

CLK1_ON

VDD2

CLK1OUT

VSS2

CLK2OUT

VDD3

CLK2_ON

SEL2

VSS3

REFOUT

I/O

–

I

–

O

I

–

O

–

O

–

I

–

O

Supply voltage 1

Master clock input (27MHz constant input)

Supply ground 1

Clock output 3 (36/45/48.6MHz switchable output)

Output clock enable 3 (HIGH = enable, LOW = disable)

Output select 1

Output clock enable 1 (HIGH = enable, LOW = disable)

Supply voltage 2

Clock output 1 (22.5792MHz constant output)

Supply ground 2

Clock output 1 (48MHz constant output)

Supply voltage 3

Output clock enable 3 (HIGH = enable, LOW = disable)

Output select 2

Supply ground 3

Master clock output (27MHz constant output)

Description

NIPPON PRECISION CIRCUITS INC.—2

SM8720AV

ABSOLUTE MAXIMUM RATINGS

V

DD

= (V

DD1

, V

DD2

, V

DD3

), V

SS

= (V

SS1

, V

SS2

, V

SS3

) unless otherwise noted.

Parameter

Supply voltage range

Supply voltage deviation

Input voltage range

Output voltage range

Power dissipation

Storage temperature range

Symbol

V

DD1

, V

DD2

, V

DD3

V

DD1

−

V

DD2

, V

DD1

−

V

DD3

,

V

DD2

−

V

DD3

V

IN

V

OUT

P

D

T

STG

Rating

−

0.3 to 6.5

±0.1

−

0.3 to V

DD

+ 0.3

−

0.3 to V

DD

+ 0.3

165

−

55 to 125

Unit

V

mW

°

C

RECOMMENDED OPERATING CONDITIONS

V

SS

= (V

SS1

, V

SS2

, V

SS3

) = 0V, unless otherwise noted.

Rating

Parameter

Supply voltage

*1

Output load capacitance 1

Output load capacitance 2

Master clock frequency

Operating temperature

Symbol

V

DD1

, V

DD2

,

V

DD3

C

L1

C

L2

f

FIN

T

OPR

REFOUT output

CLK1OUT, CLK2OUT,

CLK3OUT outputs

External clock input

Conditions

min

2.7

–

−

40

typ

–

27.0000

–

max

3.3

25

15

–

+85

V

pF

MHz

°

C

Unit

*1. The supply voltages are with reference to V

SS

= 0V.

It is recommended that the voltages applied to pins VDD1, VDD2, VDD3 be supplied from a single source.

If various voltage sources are used on pins VDD1, VDD2, VDD3, the voltage supplies should be applied simultaneously. If the timing of applying

voltage supplies varies, the device may be damaged.

ELECTRICAL CHARACTERISTICS

DC Characteristics

f

FIN

= 27.0000MHz, V

DD

= (V

DD1

, V

DD2

, V

DD3

) = 3.0 ± 0.3V, V

SS

= (V

SS1

, V

SS2

, V

SS3

) = 0V,

Ta =

−

40 to +85

°

C unless otherwise noted.

Rating

Parameter

Current consumption

Symbol

I

DD

V

IH

Input voltage

V

IL

I

IH1

Input current

I

IL1

I

IH2

I

IL2

Output voltage

V

OH

V

OL

Pins

VDD

FIN, SEL1, SEL2,

CLK1_ON,

CLK2_ON,

CLK3_ON

*1,*2

CLK1_ON,

CLK2_ON,

CLK3_ON

*1

FIN, SEL1,

SEL2

*2

All outputs

Conditions

min

V

DD

= 3.0V, Ta = 25

°

C, all

outputs operating without load

–

0.8V

DD

V

DD

= 3.0V

–

V

IN

= V

DD

V

IN

= 0V

V

IN

= V

DD

V

IN

= 0V

I

OH

=

−

2mA

I

OL

= 2mA

–

−

1

–

−

1

V

DD

−

0.4

–

30

–

0.2V

DD

80

–

1

–

0.4

V

µA

V

typ

21

–

max

28

–

mA

V

Unit

*1. CLK1_ON, CLK2_ON, CLK3_ON pins have Schmitt-trigger inputs with internal pull-down resistance.

*2. SEL1, SEL2 pins have Schmitt-trigger inputs.

NIPPON PRECISION CIRCUITS INC.—3

SM8720AV

AC Characteristics

f

FIN

= 27.0000MHz, V

DD

= (V

DD1

, V

DD2

, V

DD3

) = 3.0 ± 0.3V, V

SS

= (V

SS1

, V

SS2

, V

SS3

) = 0V,

Ta =

−

40 to +85

°

C unless otherwise noted.

Rating

Parameter

External input clock

frequency

External clock duty cycle

*1

Symbol

Pins

Conditions

min

f

FIN

Dt

FIN

REFOUT

Output clock rise time

*2

t

r

All outputs excluding

REFOUT

Output clock fall time

*2

t

f

All outputs excluding

REFOUT

Output clock jitter

(peak-to-peak)

*3,*4

t

jitter

CLK1OUT,

CLK3OUT

CLK2OUT

REFOUT

*2,*5

Output clock duty cycle

Dt

All outputs excluding

REFOUT

*2

Power-up time

*2,*6

t

P

All outputs excluding

REFOUT

External clock input

Ta = 25

°

C, V

I

= 0.5V

DD

,

external clock input

C

L

= 25pF, V

OL

= 0.2V

DD

to

V

OH

= 0.8V

DD

transition

C

L

= 15pF, V

OL

= 0.2V

DD

to

V

OH

= 0.8V

DD

transition

C

L

= 25pF, V

OH

= 0.8V

DD

to

V

OL

= 0.2V

DD

transition

C

L

= 15pF, V

OH

= 0.8V

DD

to

V

OL

= 0.2V

DD

transition

Ta = 25°C, C

L

= 25pF,

V

O

= 0.5V

DD

Ta = 25°C, C

L

= 15pF,

V

O

= 0.5V

DD

Ta = 25°C, C

L

= 15pF,

V

O

= 0.5V

DD

Ta = 25°C, C

L

= 25pF,

V

O

= 0.5V

DD

Ta = 25°C, C

L

= 15pF,

V

O

= 0.5V

DD

–

45

–

45

–

typ

27.0000

50

–

140

220

50

1

max

–

55

3.0

4.0

3.0

4.0

200

350

500

55

5

MHz

%

ns

ps

%

ms

Unit

*1. When using an external clock input, it is recommended that FIN duty cycle = 50%, clock signal amplitude = V

DD

level. Note that the input signal

voltage amplitude should not exceed the absolute maximum rating, otherwise the device may be damaged.

*2. Measured using the circuit shown in ﬁgure 1 on the NPC standard evaluation board.

*3. Measured using the circuit shown in ﬁgure 2 on the NPC standard evaluation board.

*4. Measured using master clock input on FIN with

≤80ps

(peak-to-peak) jitter.

*5. Measured using master clock input on FIN with duty cycle = 50%, clock signal amplitude = V

DD

level.

*6. The power-up time is the time from supply OFF/ON transition or enable LOW/HIGH transition until each output clock reaches its designated

frequency to within ±0.1%.

27MHz

DUT

Active Probe

(HP1152A)

Oscilloscope

(Infinium

HP54845A)

Frequency &

Time Interval

Analyzer

(HP5371A)

DUT

Active Probe

(HP54701A)

DUT:Device under test

Passive Probe

(HP10435A)

Oscilloscope

(HP54720D

+HP54721A)

Jitter

Measurement

System

(ASA, M1)

DUT:Device under test

Figure 1. Measurement circuit 1

Figure 2. Measurement circuit 2

NIPPON PRECISION CIRCUITS INC.—4

SM8720AV

FUNCTIONAL DESCRIPTION

27MHz Master Clock

The 27MHz master clock is an external clock input on pin FIN as shown in ﬁgure 3. It is recommended that the

master clock have 27.0000MHz frequency, 50% duty, and V

DD

level amplitude.

Note that the FIN input clock amplitude voltage level should not exceed the absolute maximum rating, other-

wise the device may be damaged.

External Clock

FIN (Pin 2)

Internal

Circuits

REFOUT (Pin 16)

Figure 3. External clock input

Output Clock Frequency

The SM8720AV generates 3 output clocks with frequency 22.5792MHz (CLK1OUT), 48MHz (CLK2OUT),

and 36/45/48.6MHz (CLK3OUT), derived from the master clock. In addition, the 27MHz master clock is out-

put on REFOUT. A list of the supported clock frequency and control settings is shown in table 1.

Table 1. Output clock frequency (27.0000MHz master clock frequency)

Output clock frequency [MHz]

CLK3OUT (Pin 4)

CLK1_ON

(Pin 7)

CLK2_ON

(Pin 13)

CLK3_ON

(Pin 5)

REFOUT

(Pin 16)

CLK1OUT

(Pin 9)

CLK2OUT

(Pin 11)

SEL1 = H

(Pin 6)

SEL2 = L

(Pin 14)

36.0000

L

SEL1 = L

(Pin 6)

SEL2 = L

(Pin 14)

45.0000

L

SEL1 = L

(Pin 6)

SEL2 = H

(Pin 14)

48.6000

L

H

L

H

L

H

L

H

L

27.0000

22.5792

L

22.5792

L

22.5792

L

22.5792

L

48.0000

L

48.0000

L

NIPPON PRECISION CIRCUITS INC.—5

SM8720AV

SM8720AV概述

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