HV220/HV20220/HV20320
Low Charge Injection
8-Channel High Voltage Analog Switches
Features
HVCMOS
®
technology for high performance
Very low quiescent power dissipation – 10µA
Output on-resistance typically 22 ohms
Low parasitic capacitances
DC to 10MHz analog signal frequency
-60dB typical output off isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
Flexible high voltage supplies
General Description
These devices are low charge injection 8-channel high-voltage
analog switch integrated circuits (ICs) intended for use in
applications requiring high voltage switching controlled by low
voltage control signals, such as ultrasound imaging and print-
ers. Input data is shifted into an 8-bit shift register which can
then be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, Latch Enable Bar (LE) should be left high
until all bits are clocked in. Using HVCMOS technology, these
switches combine high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high voltage
analog signals.
These ICs are suitable for various combinations of high voltage
supplies, e.g., V
PP
/V
NN
: +50V/–150V, or +100V/–100V.B
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Block Diagram
D
IN
LATCHES
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
D
LE
CL
CLK
D
LE
CL
SW1
SW2
8-Bit
Shift
Register
D
LE
CL
SW3
D
LE
CL
SW4
D
LE
CL
SW5
D
OUT
D
LE
CL
SW6
D
LE
CL
SW7
V
DD
LE
CL
V
NN
V
PP
HV220/HV20220/HV20320
Ordering Information
Package Options
Device
28-Lead PLCC
-
HV20220PJ
HV20220PJ-G
HV20320PJ
HV20320PJ-G
48-Lead LQFP/TQFP
(1.4mm)
-
HV20220FG
HV20220FG-G
-
25-Ball fpBGA
HV220GA
HV220GA-G
-
-
HV220
HV20220
HV20320
-G indicates the part is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
DD
logic power supply voltage
V
PP
- V
NN
supply voltage
V
PP
positive high voltage supply
V
NN
negative high voltage supply
Logic input voltages
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation:
28-Lead PLCC
48-Lead LQFP/ TQFP(1.4mm)
25-Ball fpBGA
Value
-0.5V to +15V
220V
-0.5V to V
NN
+200V
+0.5V to -200V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65
O
C to +150
O
C
1.2W
1.0W
1.0W
Product Marking
Top Marking
YY = Year Sealed
WW = Week Sealed
LLLLLLLLL
L = Lot Number
Bottom Marking
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
CCCCCCCC
HV20220FG
AAA
YYWW
*May be part of top marking
HV20220 FG
Top Marking
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
YY = Year Sealed
WW = Week Sealed
LLLLLLLLLL
L = Lot Number
Bottom Marking
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
CCCCCCCCCCC
YYWW
HV20220PJ
AAA
*May be part of top marking
HV20220 PJ
Operating Conditions
Symbol Parameter
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Logic power supply voltage
1,3
Top Marking
Value
4.5V to 13.2V
40V to V
NN
+200V
-40V to -160V
V
DD
-1.5V to V
DD
0V to 1.5V
V
NN
+10V to
V
PP
-10V
2
0 C to 70 C
O
O
positive high voltage supply
1,3
negative high voltage supply
1,3
High level input voltage
Low-level input voltage
Analog signal voltage peak-to-peak
Operating free air temperature
YY = Year Sealed
WW = Week Sealed
LLLLLLLLLL
L = Lot Number
Bottom Marking
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
CCCCCCCCCCC
YYWW
HV20320PJ
AAA
*May be part of top marking
HV20320 PJ
Top Marking
Notes:
1. Power up/down sequence is arbtrary except GND must be powered -up first
and powered down last.
2. V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power up/down transition.
3. Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than
1.0msec.
YYWW
HV220GA
LLLLLLLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
HV20220 GA
2
HV220/HV20220/HV20320
DC Electrical Characteristics
(Over operating conditions unless otherwise specified )
0
O
C
Sym
Parameter
Min
-
-
R
ONS
Small signal switch
on-resistance
-
-
-
-
ΔR
ONS
R
ONL
I
SOL
V
OS
I
PPQ
I
NNQ
I
PPQ
I
NNQ
I
SW
f
SW
Small signal switch
on-resistance matching
Large signal switch
on-resistance
Switch off leakage per
switch
DC offset switch off
DC offset switch on
Quiescent V
PP
supply
current
Quiescent V
NN
supply
current
Quiescent V
PP
supply
current
Quiescent V
NN
supply
current
Switch output peak current
Output switching
frequency
-
-
-
-
-
-
-
-
-
-
-
-
I
PP
Supply current
-
-
-
I
NN
Supply curent
-
-
I
DD
I
DDQ
I
SOR
I
SINK
C
IN
Logic supply average
current
Logic supply Quiescent
current
Data out source current
Data out sink current
Logic input capacitance
-
-
0.45
0.45
-
Max
30
25
25
18
23
22
20
-
5.0
300
500
-
-
-
-
3.0
-
6.5
4.0
4.0
6.5
4.0
4.0
4.0
10
-
-
10
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.45
0.45
-
+25
O
C
Typ
26
22
22
18
20
16
5.0
15
1.0
100
100
10
-10
10
-10
3.0
-
-
-
-
-
-
-
-
-
0.70
0.70
-
Max
38
27
27
24
25
25
20
-
10
300
500
50
-50
50
-50
2.0
50
7.0
5.0
5.0
7.0
5.0
5.0
4.0
10
-
-
10
+70
O
C
Units
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.40
0.40
-
Max
48
32
30
27
30
27
20
-
15
300
500
-
-
-
-
2.0
-
8.0
5.5
5.5
8.0
5.5
5.5
4.0
10
-
-
10
mA
μA
mA
mA
pF
mA
mA
%
Ω
μA
mV
mV
μA
μA
μA
μA
A
kHz
Ω
I
SIG
= 5mA
I
SIG
= 200mA
I
SIG
= 5mA
I
SIG
= 200mA
I
SIG
= 5mA
I
SIG
= 200mA
V
PP
= +40V
V
NN
= -160V
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
Conditions
I
SIG
= 5.0mA, V
PP
= +100V,
V
NN
= - 100V
V
SIG
= V
PP
-10V, I
SIG
= 1.0A
V
SIG
= V
PP
-10V, V
NN
+10V
R
L
= 100Ω
R
L
= 100kΩ
All switches off
All switches off
All switches on, I
SW
= 5.0mA
All switches on, I
SW
= 5.0mA
V
SIG
duty cycly < 0.1%
Duty cycle = 50%
V
PP
= +40V
V
NN
= -160V
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
V
PP
= +40V
V
NN
= -160V
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
f
CLK
= 5.0MHz, V
DD
= 5.0V
---
V
OUT
= V
DD
-0.7V
V
OUT
= 0.7V
---
All output
switches are
turning On
and Off at
50kHz with
no load
3
HV220/HV20220/HV20320
AC Electrical Characteristics
(Over recommended operating conditions: V
DD
= 5.0V, unless otherwise specified)
0
O
C
Sym
t
SD
t
WLE
t
DO
t
WCL
t
SU
t
H
f
CLK
t
R
, t
F
t
ON
t
OFF
dv/dt
Parameter
Min
Set up time before LE
rises
Time width of LE
Clock delay time to data
out
Time width of CL
Set up time data to clock
Hold time data from clock
Clock frequency
Clock rise and fall times
Turn on time
Turn off time
150
15
35
5.0
50
5.0
5.0
20
Maximun V
SIG
slew rate
-30
-58
-60
300
5.0
25
-
-
Output voltage spike
-
-
-
-
-
QC
Charge injection
-
-
17
50
-
-
-
-
-
-
-
-
-
5.0
25
-
-
-
-
-
-
-
-
-
20
20
K
O
K
CR
I
ID
C
SG(OFF)
C
SG(ON)
+V
SPK
-V
SPK
+V
SPK
-V
SPK
+V
SPK
-V
SPK
Off isolation
Switch crosstalk
Output switch isolation
diode current
Off capacitance SW to
GND
On capacitance SW to
GND
-30
-58
-60
150
150
150
150
15
35
Max
Min
150
150
+25
O
C
Typ
Max
+70
O
C
Units
Min
150
150
150
150
150
Max
ns
ns
ns
ns
ns
ns
5.0
50
5.0
5.0
20
20
20
-30
-58
dB
dB
300
5.0
25
-
-
-
-
-
-
-
-
-
17
50
-
-
-
-
-
-
-
-
-
pC
mV
mA
pF
pF
V/ns
MHz
ns
μs
μs
---
---
---
---
---
---
50% Duty cycle, f
DATA
= f
CLK
/2
---
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
PP
= +160V, V
NN
= -40V
V
PP
= +100V, V
NN
= -100V
V
PP
= +40V, V
NN
= -160V
f = 5.0MHz, 1kΩ/15pF load
f = 5.0MHz, 50Ω load
f = 5.0MHz, 50Ω load
300ns pulse width,
2.0% duty cycle
0V, f = 1.0MHz
0V, f = 1.0MHz
V
PP
= +40V, V
NN
= -160V,
R
LOAD
= 50Ω
V
PP
= +100V, V
NN
= -100V,
R
LOAD
= 50Ω
V
PP
= +160V, V
NN
= -40V,
R
LOAD
= 50Ω
V
PP
= +40V, V
NN
= -160V,
V
SIG
= 0V
V
PP
= +100V, V
NN
= -100V,
V
SIG
= 0V
V
PP
= +160V, V
NN
= -40V,
V
SIG
= 0V
Conditions
8.0
20
35
5.0
50
5.0
5.0
20
20
20
-33
-70
300
12
38
-
-
-
-
-
-
820
600
350
17
50
150
150
150
150
150
150
-
-
-
-60
4
HV220/HV20220/HV20320
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLR
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Hold Previous State
All Switches Off
SW0
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
D
N+1
DATA
IN
LE
50%
50%
t WLE
t
SD
50%
D
N
D
N-1
50%
CLOCK
50%
t
SU
t
t
h
50%
DD
DATA
OUT
50%
t
t ON
OFF
V
OUT
OFF
(TYP)
90%
ON
10%
50%
50%
CLR
t
WCL
5
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