DA9187.002
29 January, 2004
MAS9187
12 X 8-bit D to A Converter
•
3-pin Serial Data Interface
•
Low Voltage Output Buffer
DESCRIPTION
MAS9187 is 12-channel 8-bit DAC, designed
primarily for trimmer replacement. Device is
controlled by a simple 3-line input. The output
buffers operate in the entire voltage range from
ground to the positive power supply rail.
DAC is selected with four first bits in serial input
data (SDI-pin) and the DAC output value is set
according to the last 8 bits in serial input data.
FEATURES
•
•
•
•
•
Twelve 8-bit DACs on a single monolithic chip
Voltage level output
TSSOP 20 package
Single, low +1.8 V supply
Power-on reset
APPLICATIONS
•
•
•
High resolution monitors
Automatic gain control
Trimmer replacement
BLOCK DIAGRAM
SDI
CLK
12-bit
Shift
Register
8-bit data
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O12
O11
O10
O9
O8
O7
XCS
Address
Decoder
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
O6
O5
O4
O3
O2
O1
VREFHVREFL
VDD
GND
1 (7)
DA9187.002
29 January, 2004
PIN CONFIGURATION
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
1
2
3
4
20
19
18
17
VDD
XRESET
O12
O11
O10
O9
O8
O7
SDI
CLK
VREFH
1
O1
2
20
VDD
19
O12
18
O11
17
O10
16
O9
15
O8
14
O7
13
SDI
12
CLK
11
VREFL
O2
3
O3
4
O4
5
O5
6
O6
7
XSHDN
8
XCS
9
GND
10
MAS9187A1
YYWW
5
6
7
8
9
10
16
15
14
13
12
11
MAS9187A2
YYWW
Top view
YYWW = year, week
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MAS9187 A1
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
CLK
SDI
O7
O8
O9
O10
O11
O12
XRESET
VDD
MAS9187 A2
VREFH
O1
O2
O3
O4
O5
O6
XSHDN
XCS
GND
VREFL
CLK
SDI
O7
O8
O9
O10
O11
O12
VDD
Function
DAC output reference high voltage
DAC 1, address 0x0
DAC 2, address 0x1
DAC 3, address 0x2
DAC 4, address 0x3
DAC 5, address 0x4
DAC 6, address 0x5
Device analog part power-down signal (active low)
Device enable signal (rising edge loads data to DAC)
Device ground-pin
Data clock / DAC output low reference voltage
Serial input data / Data clock
DAC 7, address 0x6 / Serial input data
DAC 8, address 0x7 / DAC 7, address 0x6
DAC 9, address 0x8 / DAC 8, address 0x7
DAC 10, address 0x9 / DAC 9, address 0x8
DAC 11, address 0xA / DAC 10, address 0x9
DAC 12, address 0xB / DAC 11, address 0xA
Device Digital part reset – middle code preset pin/DAC
12, address 0xB
Device power supply pin
MAS9187 has two bonding options available:
•
•
MAS9187A1, where VREFL pin is bonded to GND pin and XRESET pin can be used
MAS9187A2, where XRESET pin is bonded to VDD pin and VREFL pin can be used
2 (7)
DA9187.002
29 January, 2004
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply (VDD to GND)
Input Voltage Range (any other pin)
Continuous Power Dissipation
Storage Temperature Range
-65
Symbol
VDD
Conditions
Min
-0.3
-0.3
Max
+6.0
VDD + 0.3
1000
+150
Unit
V
V
mW
°C
RECOMMENDED OPERATION CONDITIONS
Parameter
Symbol
Conditions
Min
Typ
3.6
Max
5.5
+85
Unit
V
°C
Note
1)
Supply Voltage Range
VDD
2.7
Operating Temperature
Temp
-40
Range
Note 1:
MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V
ELECTRICAL CHARACTERISTICS
(VDD = 3.0 V
±
10% or 5.0 V
±
10%, VREFH = VDD, VREFL = 0V, -40°C
≤
T
A
≤
+85°C unless otherwise noted)
DC Parameters
◆
Digital Inputs
Parameter
DAC Resolution
DAC Differential Nonlinearity Error
DAC Integral Nonlinearity Error
DAC Full-scale Error
DAC Zero Code Error
DAC Output Resistance
◆
Reference Input
Parameter
REFH Voltage Range
Symbol
N
DNL
INL
GFSE
BZSE
ROUT
Conditions
Min
-1
-1
-1
-1
Typ
8
Max
+1
+1
+1
+1
Unit
Bits
LSB
LSB
LSB
LSB
Ω
30
60
Symbol
VREFH
VREFL
RREFH
RREFL
Conditions
V
REFH
> V
REFL
V
REFH
> V
REFL
Min
0
0
5
Typ
Max
VDD
VDD
Unit
REFL Voltage Range (MAS9187A2 only)
REFH Input Resistance
REFL Input Resistance
10
10
kΩ
kΩ
3 (7)
DA9187.002
29 January, 2004
◆
Digital Input
Parameter
Digital Logic High
Digital Logic Low
Digital Input Current
◆
Power Supplies
Parameter
Power Supply Range
Supply Current
Supply Current
Shutdown Current
Symbol
VDD
IDD
IDD
ISHDN
VDD = 3.60V
VDD = 5.50V
0.5
Conditions
Min
2.7
3
Typ
Max
5.5
6
20
5
Unit
V
mA
mA
uA
Note
1)
Symbol
VIH
VIL
IIL
Conditions
Min
0.7*VDD
0.3*VDD
±
1
uA
Typ
Max
Unit
Note 1:
MAS9187Axx3 and MAS9187Axx4 minimum supply voltage 1.8 V
AC Parameters
◆
AC Characteristics
Dynamic Performance
Parameter
Power Supply Sensitivity (100Hz)
Vout Settling time (±1/2 LSB error band)
Crosstalk between adjacent outputs
Switching Characteristics
(Minimum values at +25 C, VDD = 3.60 V)
o
Symbol
PSRR
TS
CT
Conditions
Min
Typ
54
6
63
Max
Unit
dB
µs
dB
Parameter
Input Clock High Pulse Width
Input Clock Low Pulse Width
Data Setup Time
Data Hold Time
XCS Fall to First Clock Pulse Fall
XCS High Pulse Width
RESET Pulse Width
CLK Rise to XCS Rise Hold Time
XCS Rise to CLOCK Rise Setup
Symbol
TCH
TCL
TDS
TDH
TCLCL
TCSW
TRS
TCSH
TCS1
Conditions
Min
Typ
16
7
-5
5
16
22
28
22
-5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 (7)
DA9187.002
29 January, 2004
OPERATING MODES
DAC maximum output voltage is set using VREFH and VREFL pins (= 255/256 * (VREFH-VREFL)+VREFL)
(note: VREFL=GND in case of MAS9187A1). XRESET pin is used for middle code preset: DAC registers are
reset and middle code will appear at the DAC output.
Serial input data is written to SDI while XCS is low. Data is read at CLK rising edge to on-chip shift register.
Rising XCS-pin stops data reading and 12 CLK-cycles are used as the input data (4 address bits and 8 data
bits). The last 12 bits before rising XCS are used as input data.
◆
Timing diagram
SDI
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
CLK
XCS
V
OUT
APPLICATION AND TEST CIRCUIT INFORMATION
+3.0v
DAC Register Load
20
VDD
1
VREFH
MAS9187A2
8
XSHDN
O12
O11
CLK
SDI
XCS
O10
O9
O8
9
O7
O6
O5
O4
O3
19
18
17
16
15
14
7
6
5
4
3
2
Controller
Clock
Data In
Latch
12
13
100 nF
GND
10
O2
O1
VREFL
11
5 (7)
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