FemtoClock
®
Crystal-to-LVDS
Frequency Synthesizer
G
ENERAL
D
ESCRIPTION
The 844008I-01 is an 8 output LVDS Synthesizer optimized to
generate GbE/10GbE reference clock frequencies. Using a 25MHz
parallel resonant crystal, the following frequencies can be generated
based on the F_SEL pin: 125MHz or 156.25MHz. The 844008I-01
uses IDT’s 3
rd
generation low phase noise VCO technology and can
achieve <1ps typical rms phase jitter, easily meeting GbE/10GbE
jitter requirements. The 844008I-01 is packaged in a 32-pin TQFP
or 32 VFQFN packages.
844008I-01
DATASHEET
F
EATURES
• Eight LVDS outputs
• Crystal oscillator interface
• Supports the following output frequencies:
125MHz or 156.25MHz
• VCO: 625MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.38ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Input Frequency (MHz)
25MHz
25MHz
F_SEL
0
1
M Divider Value
25
25
N Divider Value
4
5
Output Frequency (MHz)
156.25
125 (default)
B
LOCK
D
IAGRAM
OEA
Pullup
QA0
nPLL_SEL
Pulldown
nQA0
QA1
1
25MHz
P
IN
A
SSIGNMENT
XTAL_OUT
nPLL_SEL
XTAL_IN
GND
V
DDA
OEA
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
F_SEL
QA3
nQA3
V
DD
GND
QB0
nQB0
MR
OEB
V
DD
32 31 30 29 28 27 26 25
QA0
nQA0
V
DD
QA1
24
23
QB3
nQB3
V
DD
QB2
nQB2
GND
QB1
nQB1
nQA1
QA2
844008I-01
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
22
21
20
19
18
17
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
0
÷4
÷5
nQA2
QA3
nQA3
nQA1
GND
QA2
nQA2
M =
÷
25 (fixed)
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
844008I-01
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm
package body
Y Package
Top View
MR
Pulldown
F_SEL
Pullup
OEB
Pullup
nQB3
844008I-01
32-Lead VFQFN
5mm x 5mm x 0.925mm pack-
age body
K Package
Top View
844008I-01 REVISION B 4/22/15
1
©2015 Integrated Device Technology, Inc.
844008I-01 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 12, 22,
27
4, 5
6, 13, 19,
29
7, 8
9
10, 11
14, 15
16
17, 18
20, 21
23, 24
25
26
28
30, 31
32
Name
QA0, nQA0
V
DD
QA1, nQA1
GND
QA2, nQA2
F_SEL
QA3, nQA3
QB0, nQB0
MR
nQB1, QB1
nQB2, QB2
nQB3, QB3
V
DDA
nPLL_SEL
OEB
XTAL_OUT,
XTAL_IN
OEA
Output
Power
Ouput
Power
Output
Input
Output
Output
Input
Output
Output
Output
Power
Input
Input
Input
Input
Pullup
Type
Description
Differential output pair. LVDS interface levels.
Core supply pins.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Frequency select pin. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs to go low and the inverted output to go high. When
Pulldown
logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVT-
TL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
Selects between the PLL and XTAL as input to the dividers. When LOW,
Pulldown selects PLL (PLL enabled). When HIGH, selects the XTAL (PLL bypassed).
LVCMOS/LVTTL interface levels.
Output enable for QB[0:3]/nQB[0:3] outputs. See Table 3B. LVCMOS/LVTTL
Pullup
interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Output enable for QA[0:3]/nQA[0:3] outputs. See Table 3A. LVCMOS/LVTTL
Pullup
interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. OEA F
UNCTION
T
ABLE
Input
OEA
0
1
Outputs
QA[0:3], nQA[0:3]
High Impedance state
Normal operation
T
ABLE
3B. OEB F
UNCTION
T
ABLE
Input
OEB
0
1
Outputs
QB[0:3], nQB[0:3]
High Impedance state
Normal operation
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
2
REVISION B 4/22/15
844008I-01 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
32 TQFP, E-Pad
32 VFQFN
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
32.2°C/W (0 mps)
37°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.20
Typical
3.3
3.3
Maximum
3.465
V
DD
275
20
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
MR, nPLL_SEL
OEA, OEB, F_SEL
MR, nPLL_SEL
OEA, OEB, F_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 3.3V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
325
1.2
Typical
Maximum
550
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
1.3
1.5
50
REVISION B 4/22/15
3
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
844008I-01 DATA SHEET
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
5
Maximum
Units
MHz
Ω
pF
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
tsk(o)
tjit(cc)
tjit(Ø)
t
R
/ t
F
Parameter
Output Frequency
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
156.25MHz, (1.875MHz - 20MHz)
20% to 80%
300
0.38
0.42
700
Test Conditions
FSEL = 0
FSEL = 1
Minimum
Typical
156.25
125
110
25
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
odc
Output Duty Cycle
47
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditons.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
4
REVISION B 4/22/15
844008I-01 DATA SHEET
T
YPICAL
P
HASE
N
OISE AT
125MH
Z
125MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.38ps (typical)
Gigabit Ethernet Filter
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
Phase Noise Result by adding a Giga-
bit Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
156.25MH
Z
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.42ps (typical)
➤
Gigabit Ethernet Filter
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
REVISION B 4/22/15
5
➤
Phase Noise Result by adding a Giga-
bit Ethernet Filter to raw data
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
➤
➤
➤
➤
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