• Provide Authentication feature by Monotonic Counter (MC) Feature
• Support clock frequency up to 104MHz
P/N: PM2571
Macronix Proprietary
Rev. 0.00, March 25, 2019
ADVANCED INFORMATION
MX77L12850F
Contents
1. FEATURES .............................................................................................................................................................. 4
2. GENERAL DESCRIPTION ..................................................................................................................................... 5
6. DATA PROTECTION................................................................................................................................................ 8
Table 1. Protected Area Sizes .....................................................................................................................9
10. POWER-ON STATE ............................................................................................................................................. 75
13. ERASE AND PROGRAMMING PERFORMANCE .............................................................................................. 84
14. DATA RETENTION .............................................................................................................................................. 84
16. ORDERING INFORMATION ................................................................................................................................ 85
17. PART NAME DESCRIPTION ............................................................................................................................... 86
18. PACKAGE INFORMATION .................................................................................................................................. 87
P/N: PM2571
Macronix Proprietary
3
Rev. 0.00, March 25, 2019
ADVANCED INFORMATION
MX77L12850F
3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO
(SERIAL MULTI I/O)
RPMC FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0 and
Mode 3
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program opera-
tions
•
128Mb: 134,217,728 x 1 bit structure or 67,108,864
x 2 bits (two I/O mode) structure or 33,554,432 x 4
bits (four I/O mode) structure
• Protocol Support
- Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Fast read for SPI mode
- Support fast clock frequency for read operation as
104MHz
- Support Fast Read, 2READ, DREAD, 4READ,
QREAD instructions
• Permanently fixed QE bit (The Quad Enable bit);
QE=1 and 4 I/O mode is always enabled.
• Equal Sectors with 4K byte each, or Equal Blocks
with 32K byte each or Equal Blocks with 64K byte
each
- Any Block can be erased individually
• Programming :
- 256byte page buffer
- Quad Input/Output page program(4PP) to enhance
program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
RPMC FEATURES
•
Support Replay Protection Monotonic Counter
(RPMC)
- Four 32-bit Monotonic counters
- Volatile HMAC Key register
- Non-volatile Root Key register
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block lock protection
- The BP0-BP3 and T/B status bits define the size
of the area to be protected against program and
erase instructions
• Additional 4K bit security OTP
-
Features unique identifier
-
Factory locked identifiable, and customer lockable
•
Command Reset
•
Program/Erase Suspend and Resume operation
•
Electronic Identification
-
JEDEC 1-byte manufacturer ID and 2-byte device
ID
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and
1-byte device ID
•
Support Serial Flash Discoverable Parameters
(SFDP) mode
HARDWARE FEATURES
•
SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input/Output
• SO/SIO1
- Serial Data Input/Output
• SIO2
- Serial Data Input/Output
• SIO3
- Serial Data input/Output
• PACKAGE
- 8-pin SOP (200mil)
- 8-land WSON (6x5mm)
-
All devices are RoHS Compliant and Halogen-
free
P/N: PM2571
Macronix Proprietary
4
Rev. 0.00, March 25, 2019
ADVANCED INFORMATION
MX77L12850F
2. GENERAL DESCRIPTION
MX77L12850F is 128Mb bits Serial NOR Flash memory, which is configured as 16,777,216 x 8 internally. When it is
in two or four I/O mode, the structure becomes 67,108, 864 bits x 2 or 33,554,432 bits x 4.
MX77L12850F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus
while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial
data output (SO).
Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for ad-
dress/dummy bits input and data output.
The MX77L12850F MXSMIO
(Serial Multi I/O) provides sequential read operation on the whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX77L12850F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
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