Low Skew, 1-to-1 Differential-
to-LVCMOS/ LVTTL Fanout Buffer
83948I-147
Data Sheet
General Description
The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT-
TL Fanout Buffer. The 83948I-147 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input lev-
els. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50 series or parallel terminated transmission lines. The effective fa-
nout can be increased from 12 to 24 by utilizing the ability of the out-
puts to drive two series terminated lines.
The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V
core/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the 83948I-147 ideal for those
clock distribution applications demanding well defined performance
and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
Twelve LVCMOS/LVTTL outputs
Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Output frequency: 350MHz
Additive phase jitter, RMS: 0.14ps (typical)
Output skew: 100ps (maximum), 3.3V±5%
Part-to-part skew: 1ns (maximum), 3.3V±5%
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
Block Diagram
CLK_EN
Pin Assignment
GND
GND
V
DDO
Q0
V
DDO
D
Q
CLK_SEL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9
Q11
Q3
Q1
Q2
LVCMOS_CLK
CLK
nCLK
CLK_SEL
1
0
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
10 11 12 13 14 15 16
V
DDO
GND
V
DDO
GND
Q10
Q9
Q8
83948I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
©2016 Integrated Device Technology, Inc
1
Revision D March 30, 2016
83948I-147 Data Sheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
10, 14, 18,
22, 26, 30
Name
CLK_SEL
LVCMOS_CL
K
CLK
nCLK
CLK_EN
OE
V
DD
GND
Q11, Q10,
Q9, Q8, Q7,
Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
V
DDO
Input
Input
Input
Input
Input
Input
Power
Power
Type
Pullup
Pullup
Pullup
Pulldown
Pullup
Pullup
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, outputs are in an High-impedance state.
when HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Power supply pin.
Power supply ground.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
5
Test Conditions
Minimum
Typical
4
51
51
12
7
12
Maximum
Units
pF
k
k
pF
Function Tables
Table 3A. Clock Select Function Table
Control
Input
0
1
Clock
CLK/nCLK inputs selected
LVCMOS_CLK input selected
©2016 Integrated Device Technology, Inc
2
Revision D March 30, 2016
83948I-147 Data Sheet
Table 3B. Clock Input Function Table
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
–
–
–
–
–
–
0
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
–
–
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
–
–
Outputs
Q[0:11]
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Non-Inverting
Non-Inverting
NOTE 1: Please refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.6C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
55
Units
V
V
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
52
Units
V
V
mA
©2016 Integrated Device Technology, Inc
3
Revision D March 30, 2016
83948I-147 Data Sheet
Table 4C. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
55
Units
V
V
mA
Table 4D. DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
LVCMOS
Input High Voltage
LVCMOS
LVCMOS
V
IL
I
IN
Input Low Voltage
LVCMOS
Input Current
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
V
IN
= V
DD
or V
IN
= 3.465V or 2.625V
V
DDO
= 3.3V ± 5%
I
OH
= -24mA
V
DDO
= 2.5V ± 5%
I
OH
= -15mA
V
DDO
= 3.3V ± 5%
I
OL
= 24mA
V
OL
Output Low Voltage; NOTE 1
V
DDO
= 3.3V ± 5%
I
OL
= 12mA
V
DDO
= 2.5V ± 5%
I
OL
= 15mA
V
PP
Peak-to-Peak Input
Voltage; NOTE 2
Common Mode
Input Voltage;
NOTE 2, 3
CLK/nCLK
CLK/nCLK
V
DD
= 3.465V or 2.625V
0.15
2.4
1.8
0.55
0.30
0.6
1.3
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
300
Units
V
V
V
V
µA
V
V
V
V
V
V
V
OH
Output High Voltage; NOTE 1
V
CMR
V
DD
= 3.465V or 2.625V
GND + 0.5
V
DD
– 0.85
V
NOTE 1: Outputs capable of driving 50
transmission lines terminated with 50
to V
DDO
/2. See Parameter Measurement section,
Output
Load AC Test Circuit diagrams.
NOTE 2: V
IL
should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
4
Revision D March 30, 2016
83948I-147 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Parameter
f
MAX
t
PD
Symbol
Output Frequency
Propagation
Delay
CLK/nCLK; NOTE 1
LVCMOS_CLK;
NOTE 2
ƒ
350MHz
ƒ
350MHz
155.52MHz,
Integration Range:
12kHz – 20MHz
Measured on the Rising Edge
@ V
DDO
/2
Measured on the Rising Edge
@ V
DDO
/2
0.8V to 2V
ƒ
150MHz, Ref = CLK/nCLK
0.2
45
50
2
2
Test Conditions
Minimum
Typical
Maximum
350
4
4
Units
MHz
ns
ns
tjit
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Skew; NOTE 3, 7
Part-to-Part Skew; NOTE 4, 7
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
Clock Enable
Hold Time;
NOTE 6
CLK_EN to CLK/nCLK
CLK_EN to
LVCMOS_CLK
CLK/nCLK to CLK_EN
LVCMOS_CLK to
CLK_EN
0.14
1
ps
tsk(o)
tsk(pp)
t
R
/ t
F
odc
t
PZL,
t
PZH
t
PLZ,
t
PHZ
t
S
100
1
1.0
55
5
5
1
0
0
1
ps
ns
ns
%
ns
ns
ns
ns
ns
ns
t
H
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision D March 30, 2016
编程基础
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
