74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
Rev. 3 — 27 August 2012
Product data sheet
1. General description
The 74HC86; 74HCT86 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.
2. Features and benefits
Input levels:
For 74HC86: CMOS level
For 74HCT86: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC86N
74HCT86N
74HC86D
74HCT86D
74HC86DB
74HCT86DB
74HC86PW
74HCT86PW
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
40 C
to +125
C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
40 C
to +125
C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
NXP Semiconductors
74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
4. Functional diagram
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
2Y
6
3Y
8
4Y
11
mna787
Fig 1.
Logic symbol
1
2
=1
3
4
5
=1
6
9
10
A
Y
B
12
13
mna788
=1
8
=1
11
mna786
Fig 2.
Logic diagram (one gate)
Fig 3.
IEC logic symbol
74HC_HCT86
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 27 August 2012
2 of 16
NXP Semiconductors
74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
5. Pinning information
5.1 Pinning
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aad103
14 V
CC
13 4B
12 4A
86
11 4Y
10 3B
9
8
3A
3Y
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input nA
L
L
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Input nB
L
H
L
H
Output nY
L
H
H
L
74HC_HCT86
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 27 August 2012
3 of 16
NXP Semiconductors
74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, and (T)SSOP14
packages
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
74HC86
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
74HCT86
Min
4.5
0
0
40
-
-
-
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
74HC_HCT86
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 27 August 2012
4 of 16
NXP Semiconductors
74HC86; 74HCT86
Quad 2-input EXCLUSIVE-OR gate
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC86
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
74HCT86
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
=
20 A
I
O
=
4.0
mA
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20
A
I
O
= 5.2 mA
I
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 5.5 V
-
-
-
0
0.15
-
0.1
0.26
0.1
-
-
-
0.1
0.33
1
-
-
-
0.1
0.4
1
V
V
A
4.4
3.98
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
0.1
0.1
0.1
0.26
0.26
0.1
2.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1
20
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1
40
-
V
V
V
V
V
A
A
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HC_HCT86
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 27 August 2012
5 of 16
嵌入式系统
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