6
0.354
9.00
5
PIN #
SYMBOL
OE
Vc
GND
OUT
OUT
VDD
DESCRIPTION
Output Enable
Control Voltage
Ground
Primary Output
Complimentary
Output
COMMENT
Active High, leave floating if not used
0 ~ Vdd can be applied to pull frequency
Connect to Analog Ground
LVDS/LVPECL Primary output
LVDS/LVPECL Complimentary output
4
1
2
3
4
0.276
7.00
5
6
Bias Voltage
Apply +3.30V ±0.3V
Factory
PROG, FSEL0 & FSEL1 Configuration Pins DONOT Connect, this area needs to be masked on customer PCB
1
0.088
2.24
2
3
Recommended land Pattern
0.047
1.20
0.063
1.60
Pin # 1 Identifier
0.165
4.20
1
0.122
3.10
OE
2
VC
3
GND
5
05
0. 0
1.4
0.067
1.70
0.055
1.40
FSEL1
FSEL0
PROG
0.276
7.00
UNLESS OTHERWISE SPECIFIED:
DIMENSIONS ARE IN MM
SURFACE FINISH:
TOLERANCES:
LINEAR:
ANGULAR:
NAME
DRAWN
CHK'D
APPV'D
MFG
Q.A
MATERIAL:
DWG NO.
SAAZVAT
XXXXXX
0.118
3.00
0.102
2.60
TYP.
0.047
1.20
0.079
2.00
"This 3x7mm area should be "masked"
on the end-customer PCB and
preferably not connected to Ground.
Also, please do not route
electrical signals under
the oscillator package area".
FINISH:
DEBUR AND
BREAK SHARP
EDGES
DO NOT SCALE DRAWING
REVISION
-
VDD
OUT
OUT
6
5
4
0.110 TYP.
2.80
SIGNATURE
DATE
30332 Esperanza, Rancho Santa margarita, California 92688
TITLE:
-
ASGTX
SHEET 1 OF 1
A3
WEIGHT:
SCALE:8:1
FPGA/CPLD
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