UT1553B BCRT
F
EATURES
p
Comprehensive MIL-STD-1553B dual-redundant
p
p
p
p
p
Bus Controller (BC) and Remote Terminal
(RT) functions
MIL-STD-1773 compatible
Multiple message processing capability in BC and
RT modes
Time-tagging and message logging in RT mode
Automatic polling and intermessage delay in
BC mode
Programmable interrupt scheme and internally
generated interrupt history list
p
Register-oriented architecture to enhance
p
p
p
p
p
p
programmability
DMA memory interface with 64K addressability
Internal self-test
Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
The UT1553B BCRT is not available radiation-harden
ed
Packaged in 84-pin pingrid array, 84- and 132-lead
flatpack, 84-lead leadless chip carrier packages
Standard Microcircuit Drawing 5962-88628 available
- QML Q and V compliant
REGISTERS
MASTER
RESET
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
INTERRUPT
HANDLER
CONTROL
STATUS
CURRENT BC BLOCK/
RT DESCRIPTOR SPACE
POLLING COMPARE
BC PROTOCOL
& MESSAGE
HANDLER
BUILT-IN-TEST WORD
CURRENT COMMAND
INTERRUPT LOG
LIST POINTER
HIGH-PRIORITY
INTERRUPT ENABLE
16
RT PROTOCOL
& MESSAGE
HANDLER
BUILT-
IN-
TEST
16
HIGH-PRIORITY
INTERRUPT STATUS/RESET
STANDARD INTERRUPT
ENABLE
RT ADDRESS
BUILT-IN-TEST
START COMMAND
PROGRAMMED RESET
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
16
16
DATA
ADDRESS
RT TIMER TAG
RESET COMMAND
12MHZ
CLOCK &
RESET
LOGIC
1553
DATA
CHANNEL
A
1553
DATA
CHANNEL
B
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
SERIAL to
PARALLEL-
CONVER-
SION
PARALLEL-
TO-SERIAL
CONVER-
SION
16
BUS
TRANSFER
LOGIC
16
TIMERON
TIMEOUT
ADDRESS
GENERATOR
16
DMA/CPU
CONTROL
16
Figure 1. BCRT Block Diagram
BCRT-1
Table of Contents
1.0
INTRODUCTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
2.0
3.0
4.0
5.0
Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
PIN IDENTIFICATION AND DESCRIPTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
INTERNAL REGISTERS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SYSTEM OVERVIEW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SYSTEM INTERFACE.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
5.2
5.3
5.4
5.5
6.0
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CPU Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
REMOTE TERMINAL ARCHITECTURE.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
6.2
6.3
7.0
RT Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1.1 RT Subaddress Descriptor Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .22
6.1.2 Message Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
BUS CONTROLLER ARCHITECTURE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
7.2
7.3
7.4
7.5
8.0
9.0
10.0
11.0
12.0
BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EXCEPTION HANDLING AND INTERRUPT LOGGING
. . . . . . . . . . . . . . . . . . . . . . . . 34
MAXIMUM AND RECOMMENDED OPERATING CONDITIONS
. . . . . . . . . . . . . . . . 37
DC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC ELECTRICAL CHARACTERISTICS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PACKAGE OUTLINE DRAWINGS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
BCRT-2
1.0 I
NTRODUCTION
The monolithic CMOS UT1553B BCRT provides the
system designer with an intelligent solution to
MIL-STD-1553B multiplexed serial data bus design
problems. The UT1553B BCRT is a single-chip device that
implements two of the defined MIL-STD-1553B functions
- Bus Controller and Remote Terminal. Designed to reduce
host CPU overhead, the BCRT’s powerful state machines
automatically execute message transfers, provide interrupts,
and generate status information. Multiple registers offer
many programmable functions as well as extensive
information for host use. In the BC mode, the BCRT uses a
linked-list message scheme to provide the host with
message chaining capability. The BCRT enhances memory
use by supporting variable-size, relocatable data blocks. In
the RT mode, the BCRT implements time-tagging and
message history functions. It also supports multiple (up to
128) message buffering and variable length messages to
any subaddress.
The UT1553B BCRT is an intelligent, versatile, and easy to
implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRT is programmable to index or buffer messages on
a subaddress-by-subaddress basis. The BCRT, which can
index as many as 128 messages, can also assert an interrupt
when either the selected number of messages is reached or
every time a specified subaddress is accessed.
Variable Space Allocation
The BCRT can use as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRT provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRT stores/retrieves, by subaddress, all messages in
the order in which they are transacted.
Sequential Message Status Information
The BCRT provides message validity, time-tag, and word-
count information, and stores it sequentially in a separate,
cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRT provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRT autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRT can delay a
host-specified time before executing the next message
in sequence.
Automatic Polling
When polling, the BCRT interrogates the remote terminals
and then compares their status word responses to the
contents of the Polling Compare
Register. The BCRT can interrupt the host CPU if an
erroneous remote terminal status word response occurs.
Automatic Retry
The BCRT can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRT can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRT provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is program- mable.
Variable Space Allocation
The BCRT uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRT provides
flexible data placement and convenient access.
BCRT-3
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
