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OX16CF950: 产品描述LOW COST ASYNCHRONOUS 16 BIT CARD; 文件大小751KB，共60页; 制造商ETC

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OX16CF950概述

LOW COST ASYNCHRONOUS 16 BIT CARD

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OXCF950

DATA SHEET

EATURES

•

Single full-duplex asynchronous channel

128-byte deep transmitter / receiver FIFO

Fully software compatible with industry standard

16C550 type UARTs

Readable FIFO levels

System clock up to 60MHz at 5V, 50 MHz at 3.3V

Flexible clock prescaler from 1 to 31.875

9-bit data framing as well as 5,6,7 and 8

Detection of bad data in the receiver FIFO

Automated in-band flow control using programmable

Xon/Xoff characters

Transmitter and receiver can be disabled

Low power CMOS

3.3V / 5V operation

•

Programmable by external Microwire

EEPROM

(EEPROM programmed via Oxford Semiconductor

utilities).

Extremely low power consumption by use of

asynchronous UART core and power down (sleep)

modes

Ultra small 48 pin TQFP package.

Supports all UART types 450 up to 950 (fully

programmable)

CF+ Compliant (Revision 1.4).

16-bit PC Card Compliant (PCMCIA Revision 7.1)

8 bit Local Bus interface included for PCMCIA

applications

2 Multi- purpose I/O pins which can be configured as

interrupt inputs

ESCRIPTION

The OXCF950 is a low cost asynchronous 16-bit PC card

(henceforth referred to as PCMCIA) or Compact Flash

(henceforth referred to as CF) UART (and Local Bus)

device. Local Bus Selection is performed by use of a

MODE pin. Note that Local Bus mode uses indirect

addressing, which is only supported by PCMCIA.

The 3.3V / 5V technology has been selected to allow the

device to be used in both high and low voltage

environments, as stated in the PCMCIA specification. Note

that when the OXCF950 is operating at 3.3V, its I/O is not

5V tolerant.

The EEPROM interface allows the programming of the

Attribute Memory, UART and Local Configuration Registers

during power up or hard/soft reset. This allows different

card manufacturers to modify the information contained in

the Attribute memory or UART/registers as required, for

example PC-Card ID value.

A number of power-down modes are included to keep

power consumption to a minimum. Such features include

clock division (fully programmable) and sleep modes when

a function of the OXCF950 is not being used.

The OXCF950 contains a single-channel ultra-high

performance UART offering data rates up to 15Mbps (at

5V) and 128-deep transmitter and receiver FIFOs. Deep

FIFOs reduce CPU overhead and allow utilisation of higher

data rates.

It is software compatible with the widely used industry-

standard 16C550 type devices and compatibles, as well as

other OX16C95x family devices.

In addition to increased performance and FIFO size, the

OXCF950 also provides enhanced features including

improved flow control. Automated software flow control

using Xon/Xoff and automated hardware flow control using

CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow

control and interrupt thresholds are fully programmable and

readable, enabling programmers to fine- tune the

performance of their system. FIFO levels are readable to

facilitate fast driver applications.

The addition of software reset enables recovery from

unforeseen error conditions allowing drivers to restart

gracefully. The OXCF950 supports 9-bit data frames used

in multi-drop industrial protocols. It also offers multiple

external clock options for isochronous applications, e.g.

ISDN, xDSL.

The OXCF950 also incorporates a bridge to an 8 bit Local

Bus in Local Bus Mode. It allows card developers to

expand the capabilities of their products by adding

peripherals to this bus. In addition, two user IO pins are

included to enhance external device control. These IO pins

can also be configured as interrupt inputs.

Oxford Semiconductor Ltd.

25 Milton Park, Abingdon, Oxon, OX14 4SH, UK

Tel: +44 (0)1235 824900

Oxford Semiconductor 2001 .

DATA SHEET .

CONFIDENTIAL .

OXFORD SEMICONDUCTOR LTD.

OXCF950 DATA SHEET V1.1

ONTENTS

FEATURES.....................................................................................................................................................................................1

DESCRIPTION...............................................................................................................................................................................1

CONTENTS.....................................................................................................................................................................................2

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

5.3.2

5.3.3

5.4

5.4.1

5.4.2

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.6

5.6.1

5.6.2

BLOCK DIAGRAM ..............................................................................................................................................................5

PIN INFORMATION ............................................................................................................................................................ 6

PIN DESCRIPTIONS ..........................................................................................................................................................6

CONFIGURATION & OPERATION...............................................................................................................................9

PCMCIA / CF TARGET CONTROLLER....................................................................................................................10

OPERATION........................................................................................................................................................................ 10

CONFIGURATION SPACE (CARD INFORMATION STRUCTURE) ................................................................................. 10

LOCAL BUS MODE SPACE MAP .................................................................................................................................. 10

NORMAL MODE SPACE MAP....................................................................................................................................... 11

ACCESS TO IO FUNCTION ............................................................................................................................................... 11

ACCESS TO INTERNAL UART...................................................................................................................................... 11

ACCESS TO LOCAL BUS .............................................................................................................................................. 11

ACCESSING LOCAL CONFIGURATION REGISTERS ................................................................................................. 12

CF / PCMCIA INTERRUPT................................................................................................................................................. 14

INTERRUPT GENERATION ........................................................................................................................................... 14

INTERRUPT SOURCES................................................................................................................................................. 15

CF/PCMCIA FUNCTION CONFIGURATION REGISTERS ............................................................................................... 15

CONFIGURATION OPTIONS REGISTER ‘COR’ (OF FSET 0XF8) ............................................................................... 16

CONFIGURATION STATUS REGISTER ‘C SR’ (OFFSET 0XFA) ................................................................................. 16

PIN REPLACEMENT REGISTER ‘PRR’ (OFFSET 0 XFC) ............................................................................................ 17

SOCKET AND COPY REGISTER ‘SCR’ (OFFSET 0XFE) ............................................................................................ 18

CARD INFORMATION STRUCTURE................................................................................................................................. 19

LOCAL BUS MODE......................................................................................................................................................... 19

NORMAL MODE............................................................................................................................................................. 20

MODE SELECTION............................................................................................................................................................. 23

450 MODE....................................................................................................................................................................... 23

550 MODE....................................................................................................................................................................... 23

750 MODE....................................................................................................................................................................... 23

650 MODE....................................................................................................................................................................... 23

950 MODE....................................................................................................................................................................... 23

REGISTER DESCRIPTION TABLES ................................................................................................................................. 25

RESET CONFIGURATION ................................................................................................................................................. 28

HOST RESET .................................................................................................................................................................. 28

SOFTWARE RESET ....................................................................................................................................................... 28

TRANSMITTER & RECEIVER FIFOS................................................................................................................................ 28

FIFO CONTROL REGISTER ‘FCR’................................................................................................................................ 29

LINE CONTROL & STATUS............................................................................................................................................... 30

FALSE START BIT DETECTION .................................................................................................................................... 30

LINE CONTROL REGISTER ‘LCR’ ................................................................................................................................ 30

LINE STATUS REGISTER ‘LSR’.................................................................................................................................... 30

INTERRUPTS & SLEEP MODE ......................................................................................................................................... 32

INTERRUPT ENABLE REGISTER ‘IER’ ........................................................................................................................ 32

INTERRUPT STATUS REGISTER ‘ISR’ ........................................................................................................................ 33

Page 2

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.3.1

6.3.2

6.4

6.4.1

6.5

6.5.1

6.5.2

6.5.3

6.6

6.6.1

6.6.2

INTERNAL 950 UART......................................................................................................................................................23

OXFORD SEMICONDUCTOR LTD.

6.6.3

6.6.4

6.7

6.7.1

6.7.2

6.8

6.8.1

6.8.2

6.9

6.9.1

6.9.2

6.9.3

6.9.4

6.10

6.10.1

6.10.2

6.10.3

6.10.4

6.10.5

6.10.6

6.10.7

6.11

6.11.1

6.11.2

6.11.3

6.11.4

6.11.5

6.11.6

6.11.7

6.11.8

6.11.9

6.11.10

6.11.11

6.11.12

6.11.13

6.11.14

6.11.15

6.11.16

OXCF950 DATA SHEET V1.1

INTERRUPT DESCRIPTION .......................................................................................................................................... 33

SLEEP MODE ................................................................................................................................................................. 34

MODEM INTERFACE......................................................................................................................................................... 34

MODEM CONTROL REGISTER ‘MCR’.......................................................................................................................... 34

MODEM STATUS REGISTER ‘MSR’............................................................................................................................. 35

OTHER STANDARD REGISTERS ..................................................................................................................................... 35

DIVISOR LATCH REGISTERS ‘DLL & DLM’ ................................................................................................................. 35

SCRATCH PAD REGISTER ‘SPR’................................................................................................................................. 35

AUTOMATIC FLOW CONTROL......................................................................................................................................... 35

ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................... 35

SPECIAL CHARACTER DETECTION............................................................................................................................ 37

AUTOMATIC IN-BAND FLOW CONTROL ..................................................................................................................... 37

AUTOMATIC OUT-OF-BAND FLOW CONTROL........................................................................................................... 37

BAUD RATE GENERATION............................................................................................................................................... 37

GENERAL OPERATION ................................................................................................................................................. 37

CLOCK PRESCALER REGISTER ‘CPR’ ....................................................................................................................... 38

TIMES CLOCK REGISTER ‘TCR’................................................................................................................................... 38

INPUT CLOCK OPTIONS ............................................................................................................................................... 39

TTL CLOCK MODULE .................................................................................................................................................... 40

EXTERNAL 1X CLOCK MODE....................................................................................................................................... 40

CRYSTAL OSCILLATOR CIRCUIT ................................................................................................................................ 40

ADDITIONAL FEATURES .................................................................................................................................................. 40

ADDITIONAL STATUS REGISTER ‘ASR’...................................................................................................................... 40

FIFO FILL LEVELS ‘TFL & RFL’..................................................................................................................................... 41

ADDITIONAL CONTROL REGISTER ‘ACR’.................................................................................................................. 41

TRANSMITTER TRIGGER LEVEL ‘TTL’ ........................................................................................................................ 42

RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ........................................................................................................ 42

FLOW CONTROL LEVELS ‘FCL & FCH’ ....................................................................................................................... 42

DEVICE IDENTIFICATION REGISTERS ....................................................................................................................... 43

CLOCK SELECT REGISTER ‘CKS’ ............................................................................................................................... 43

NINE-BIT MODE REGISTER ‘NMR’............................................................................................................................... 43

MODEM DISABLE MASK ‘MDM’ .................................................................................................................................... 44

READABLE FCR ‘RFC’................................................................................................................................................... 45

GOOD-DATA STATUS REGISTER ‘GDS’ ..................................................................................................................... 45

DMA STATUS REGISTER ‘DMS’................................................................................................................................... 45

PORT INDEX REGISTER ‘PIX’ ....................................................................................................................................... 45

CLOCK ALTERATION REGISTER ‘CKA’....................................................................................................................... 45

MISC DATA REGISTER ................................................................................................................................................. 45

EEPROM DATA ORGANISA

TION ..................................................................................................................................... 46

ZONE 0 : HEADER.............................................................................................................................................................. 46

ZONE1 : CARD INFORMATION STRUCTURE ................................................................................................................. 47

ZONE 2 : LOCAL REGISTER CONFIGURATION............................................................................................................. 47

ZONE 3 : FUNCTION AC CESS (UART) ............................................................................................................................ 48

7.1

7.2

7.3

7.4

7.5

SERIAL EEPROM SPECIFICATION..........................................................................................................................46

9.1

9.2

OPERATING CONDITIONS...........................................................................................................................................49

DC ELECTRICAL CHARACTERISTICS ...................................................................................................................50

5V OPERATION .................................................................................................................................................................. 50

3V OPERATION .................................................................................................................................................................. 51

COMMON MEMORY ACCESS........................................................................................................................................... 52

ATTRIBUTE MEMORY ACCESS....................................................................................................................................... 53

I/O ACCESS........................................................................................................................................................................ 54

LOCAL BUS ACCESS........................................................................................................................................................ 55

Page 3

10.1

10.2

10.3

10.4

TIMING WAVEFORMS / AC CHARACTERISTICS...........................................................................................52

OX16CF950

OX16CF950概述

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