74ABT125
Quad buffer; 3-state
Rev. 7 — 25 November 2015
Product data sheet
1. General description
The 74ABT125 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device
features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling one of the
3-state outputs.
2. Features and benefits
Quad bus interface
3-state buffers
Live insertion and extraction permitted
Output capability: HIGH
32
mA; LOW +64 mA
Power-up 3-state
Inputs are disabled during 3-state mode
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74ABT125D
74ABT125DB
74ABT125PW
74ABT125BQ
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Name
SO14
SSOP14
TSSOP14
DHVQFN14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
Version
SOT108-1
SOT337-1
SOT402-1
SOT762-1
Type number
NXP Semiconductors
74ABT125
Quad buffer; 3-state
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one buffer)
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
74ABT125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 25 November 2015
2 of 15
NXP Semiconductors
74ABT125
Quad buffer; 3-state
5.2 Pin description
Table 2.
Symbol
1OE to 4OE
1A to 4A
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 10, 13
2, 5, 9, 12
3, 6, 8, 11
7
14
Description
output enable input (active LOW)
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Inputs
nOE
L
L
H
[1]
Function selection
[1]
Output
nA
L
H
X
nY
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
total power dissipation
Conditions
Min
0.5
1.2
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
500
Unit
V
V
V
mA
mA
mA
C
C
mW
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[2]
0.5
18
50
-
-
65
-
T
amb
=
40 C
to +85
C
[3]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
SO14 packages: above 70
C
P
tot
derate linearly with 8 mW/K
SSOP14 and TSSOP14 packages: above 60
C
P
tot
derate linearly with 5.5 mW/K
DHVQFN14 packages: above 60
C
P
tot
derate linearly with 4.5 mW/K
74ABT125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 25 November 2015
3 of 15
NXP Semiconductors
74ABT125
Quad buffer; 3-state
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
32
-
-
40
Max
5.5
V
CC
-
0.8
-
64
10
+85
Unit
V
V
V
V
mA
mA
ns/V
C
9. Static characteristics
Table 6.
Symbol
V
IK
V
OH
Static characteristics
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
I
I
I
OFF
I
O(pu/pd)
I
OZ
LOW-level output
voltage
input leakage current
power-off leakage
current
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0.0 V; V
I
or V
O
4.5 V
[1]
25
C
Typ
0.9
2.9
3.4
2.4
0.35
0.01
5.0
5.0
Max
1.2
-
-
-
0.55
1.0
100
50
-
2.5
3.0
2.0
-
-
-
-
40 C
to +85
C
Unit
Min
-
2.5
3.0
2.0
-
-
-
-
Max
1.2
-
-
-
0.55
1.0
100
50
V
V
V
V
V
A
A
A
power-up/power-down V
CC
= 2.1 V; V
O
= 0.5 V;
output current
V
I
= GND or V
CC
; OE = don’t care
OFF-state output
current
V
CC
= 5.5 V; V
I
= V
IL
or V
IH
V
O
= 2.7 V
V
O
= 0.5 V
HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state
outputs LOW-state
outputs disabled
-
-
-
[2]
1.0
1.0
5.0
100
65
12
65
50
50
50
180
250
15
250
-
-
-
50
-
-
-
50
50
50
180
250
30
50
A
A
A
mA
A
mA
A
I
CEX
I
O
I
CC
output high leakage
current
output current
supply current
50
-
-
-
74ABT125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 25 November 2015
4 of 15
NXP Semiconductors
74ABT125
Quad buffer; 3-state
Table 6.
Symbol
I
CC
Static characteristics
…continued
Parameter
additional supply
current
Conditions
Min
per control pin; V
CC
= 5.5 V;
one control input at 3.4 V, other
inputs at V
CC
or GND
outputs enabled
outputs disabled
one enable input at 3.4 V and other
inputs at V
CC
or GND; outputs
disabled
[3]
25
C
Typ
Max
40 C
to +85
C
Unit
Min
Max
-
-
-
0.5
50
0.5
1.5
250
1.5
-
-
-
1.5
250
1.5
mA
mA
mA
C
I
C
O
[1]
[2]
[3]
input capacitance
output capacitance
V
I
= 0 V or V
CC
outputs disabled; V
O
= 0 V or V
CC
-
-
4
7
-
-
-
-
-
-
pF
pF
This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V
10 %,
a transition time of up to 100
s
is permitted.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V. Test circuit is shown in
Figure 8.
Symbol Parameter
Conditions
25
C;
V
CC
= 5.0 V
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
OFF-state to HIGH
propagation delay
OFF-state to LOW
propagation delay
HIGH to OFF-state
propagation delay
LOW to OFF-state
propagation delay
nA to nY, see
Figure 6
nA to nY; see
Figure 6
nOE to nY; see
Figure 7
nOE to nY; see
Figure 7
nOE to nY; see
Figure 7
nOE to nY; see
Figure 7
1.0
1.0
1.0
1.0
1.0
1.5
Typ
2.8
3.1
3.2
4.2
4.1
2.8
Max
4.1
4.6
5.0
6.2
5.4
5.0
40 C
to +85
C;
Unit
V
CC
= 5.0 V
0.5 V
Min
1.0
1.0
1.0
1.0
1.0
1.5
Max
4.6
4.9
5.9
6.8
6.2
5.5
ns
ns
ns
ns
ns
ns
74ABT125
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 25 November 2015
5 of 15
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