M95M04-DR
Datasheet
4-Mbit serial SPI bus EEPROM
Features
SO8N (MN)
150 mil width
•
•
•
TSSOP8 (DW)
169 mil width
•
•
WLCSP (2.809 × 1.863 mm)
Compatible with the serial peripheral interface (SPI) bus
Memory array
–
4 Mbit (512 Kbytes) of EEPROM
–
Page size: 512 bytes
–
Additional write lockable page (identification page)
Write time
–
Byte write within 5 ms
–
Page write within 5 ms
Write protect
–
quarter array
–
half array
–
whole memory array
Max clock frequency:
–
10 MHz for V
CC
≥ 2.5 V
–
5 MHz for V
CC
≥ 1.8 V
Single supply voltage: 1.8 V to 5.5 V
Operating temperature range: from -40 °C up to +85 °C
Enhanced ESD protection (up to 4 kV in human body model)
More than 4 million write cycles
More than 40-year data retention
Packages
–
SO8N (ECOPACK2)
–
TSSOP8 (ECOPACK2)
–
WLCSP (ECOPACK2)
Product status link
M95M04-DR
•
•
•
•
•
•
DS12179
-
Rev 2
-
February 2021
For further information contact your local STMicroelectronics sales office.
www.st.com
M95M04-DR
Description
1
Description
The M95M04-DR device is electrically erasable programmable memory (EEPROM) organized as 524288 x 8 bits,
accessed through the SPI bus.
The M95M04-DR can operate with a supply range from 1.8 to 5.5 V, and is guaranteed over the -40 °C/+85 °C
temperature range.
The M95M04-DR offer an additional page, named the identification page (512 bytes). The identification page can
be used to store sensitive application parameters that can be (later) permanently locked in read-only mode.
Figure 1.
Logic diagram
V
CC
D
C
S
W
HOLD
V
SS
MS45413V1
M95xxx
Q
The SPI bus signals are C, D and Q, as shown in
Figure 1
and
Table 1.
The device is selected when Chip select
(S) is driven low. Communications with the device can be interrupted when the HOLD is driven low.
Table 1.
Signal names
Signal name
C
D
Q
S
W
HOLD
V
CC
V
SS
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
Function
Input
Input
Output
Input
Input
Input
-
-
Direction
DS12179
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Rev 2
page 2/44
M95M04-DR
Description
Figure 2.
8-pin package connections (top view)
M95xxx
S
Q
W
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
C
D
MS51579V1
1.
See
Section 10 Package information
for package dimensions, and how to identify pin 1.
Figure 3.
WLCSP connections
4 3
2 1
A
B
A
B
1 2
3 4
C
D
Bump side view
C
D
Top view (bumps underneath)
MS38243V1
Table 2.
Signals vs. bump position
Position
1
2
3
4
A
-
V
CC
S
-
B
-
HOLD
-
Q
C
C
-
-
W
D
-
D
V
SS
-
DS12179
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Rev 2
page 3/44
M95M04-DR
Signal description
3
Signal description
During all operations, V
CC
must be held stable and within the specified valid range: V
CC
(min) to V
CC
(max).
All of the input and output signals must be held high or low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
, as
specified in
Section 9 DC and AC parameters).
These signals are described next.
3.1
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).
3.2
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data
to be written. Values are latched on the rising edge of serial clock (C).
3.3
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data
input (D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) change from the falling
edge of serial clock (C).
3.4
Chip select (S)
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. The
device is in the standby power mode, unless an internal write cycle is in progress. Driving chip select (S) low
selects the device, placing it in the active power mode.
After power-up, a falling edge on chip select (S) is required prior to the start of any instruction.
3.5
Hold (HOLD)
The hold (HOLD) signal is used to pause any serial communications with the device without deselecting the
device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock
(C) are "Don’t care".
To start the hold condition, the device must be selected, with chip select (S) driven low.
3.6
Write protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write
instructions (as specified by the values in the BP1 and BP0 bits of the Status register).
This pin must be driven either high or low, and must be stable during all Write instructions.
3.7
V
CC
supply voltage
V
CC
is the supply voltage.
3.8
V
SS
ground
V
SS
is the reference for all signals, including the V
CC
supply voltage.
DS12179
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Rev 2
page 5/44
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