AS4C512M16D3LB
512M x 16 bit DDR3L Synchronous DRAM (SDRAM)
Features
Standard Compliant
Power supplies: V
DD
& V
DDQ
= +1.35V
Backward compatible to V
DD
& V
DDQ
= +1.5V ±0.075V
Operating temperature:
Commercial:
T
C
= 0~95°C
Industrial:
T
C
= -40~95°C
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
- DQS & DQS#
JEDEC
Overview
The 8Gb Double-Data-Rate-3L DRAMs is double data
rate architecture to achieve high-speed operation. It is
internally configured as an eight bank DRAM.
The 8Gb chip is organized as 64Mbit x 16 I/Os x 8 bank
devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to
1600
Mb/
sec/pin for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point of
differential clocks (CK rising and CK# falling). All I/Os are
synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single +1.35V -0.067V /
+0.1V power supply and are available in BGA packages.
8 internal banks for concurrent operation
8n-bit prefetch architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode
registers
Additive Latency (AL): 0, CL-1, CL-2
Programmable Burst lengths: 4, 8
Burst type: Sequential / Interleave
Output Driver Impedance Control
Average refresh period
Write Leveling
ZQ Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
Package:
Two 512Mbit x 8 dies stacked (DDP)
96-ball 9 x 13.5 x 1.2mm FBGA package
ROHS Compliant -
Pb and Halogen Free
- 8192 cycles/64ms (7.8us at -40°C
≦
T
C
≦
+85 °C)
- 8192 cycles/32ms (3.9us at +85°C
≦
T
C
≦
+95°C)
Table 1. Ordering Information
Product part No
Org
Temperature
Commercial 0°C to 95°C
Max Clock (MHz)
800
800
Package
96-ball
FBGA
96-ball
FBGA
AS4C512M16D3LB-12BCN
512M x 16
AS4C512M16D3LB-12BIN
512M x 16
Industrial -40°C to 95°C
Table 2. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800
MHz
CAS Latency
11
tRCD(ns)
13.75
tRP(ns)
13.75
Confidential
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Rev.1.0
May
2019
AS4C512M16D3LB
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail
Power
applied
Figure 3. State Diagram
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
SR
SR E
X
Self
Refresh
from any
RESET
state
ZQCL
MRS
ZQ
Calibration
ZQCL,ZQCS
Idle
REF
Refreshing
E
PD X
PD
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Active
Power
Down
PD
X
PD
E
Activating
Precharge
Power
Down
Bank
Activating
RE
AD
W
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
WR
WRITE
Writing
ITE
Write = WR, WRS4, WRS8
A
RI
TE
READ
WRITE
READ
A
RE
DA
Reading
WRITE A
READ A
EA
PRE, PREA
IT
WR
RE
AD
A
Writing
PR
PR
E,
PR
EA
Reading
E,
P
RE
Automatic Sequence
Command Sequence
Precharging
A
Confidential
- 5 of 86 -
Rev.1.0 May
2019
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