AS4C512M16D3LA
Revision History
8Gbit DDR3L SDRAM
Revision
Rev 1.0
8 BANKS X
64Mbit
X
16
- Dual Die Package (DDP)
96ball
FBGA Package
Details
Preliminary datasheet
Date
Feb.
2019
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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AS4C512M16D3LA
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Specifications
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Density : 8G bits
Organization :
- 64M words x 16 bits x 8 banks
Package :
- 96-ball FBGA
- Two 512Mbit x 8 dies stacked
(DDP)
- Lead-free (RoHS compliant) and Halogen-free
Power supply : VDD, VDDQ = 1.35V (1.283V to 1.45V)
-Backward compatible to VDD, VDDQ =1.5V ± 0.075V
Data rate : 1866Mbps
2KB page size
- Row address: A0 to A15
- Column address: A0 to A9
Eight internal banks for concurrent operation
Burst lengths (BL) : 8 and 4 with Burst Chop (BC)
Burst type (BT) :
- Sequential (8, 4 with BC)
- Interleave (8, 4 with BC)
CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11, 13
CAS Write Latency (CWL) : 5, 6, 7, 8 ,9
Precharge : auto precharge option for each burst access
Driver strength : RZQ/7, RZQ/6 (RZQ = 240
Ω)
Refresh : auto-refresh, self-refresh
Refresh cycles :
- Average refresh period
7.8
μs
at
-40°C
≤
Tc
≤
+85°C
3.9
μs
at +85°C < Tc
≤
+105°C
Operating case temperature range
- Comercial Tc = 0°C to +95°C
- Industrial Tc = -40°C to +95°C
- Automotive Tc = -40°C to +105°C
Features
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Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 8 bits prefetch pipe-
lined architecture
Bi-directional differential data strobe (DQS and DQS) is transmitted/
received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center-aligned with data
for WRITEs
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask
referenced to both edges of DQS
Data mask (DM) for write data
Posted CAS by programmable additive latency for better command
and data bus efficiency
On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern read out
ZQ calibration for DQ drive and ODT
RESET pin for Power-up sequence and reset function
SRT range : Normal/extended
Programmable Output driver impedance control
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Table 1. Ordering Information
Product part No
Org
Temperature
Commercial 0°C to 95°C
Max Clock (MHz)
933
933
933
Package
96-ball
FBGA
96-ball
FBGA
96-ball
FBGA
AS4C512M16D3LA-10BCN
512M x 16
AS4C512M16D3LA-10BIN
512M x 16
Industrial -40°C to 95°C
AS4C512M16D3LA-10BAN
512M x 16
Automotive -40°C to 105°C
Table 2. Speed Grade Information
Speed Grade
DDR3-1866
Clock Frequency
933 MHz
CAS Latency
13
tRCD(ns)
13.91
tRP(ns)
13.91
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Pin Configurations
96-ball FBGA (x16 configuration)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
V
DDQ
V
SSQ
V
REFDQ
NC
ODT
NC
V
SS
V
DD
V
SS
V
DD
V
SS
2
DQU5
V
DD
DQU3
V
DDQ
V
SSQ
DQL2
DQL6
V
DDQ
V
SS
V
DD
CS
BA0
A3
A5
A7
RESET
3
DQU7
V
SS
DQU1
DMU
DQL0
DQSL
DQSL
DQL4
RAS
CAS
WE
BA2
A0
A2
A9
A13
4
5
6
7
DQU4
DQSU
DQSU
DQU0
DML
DQL1
V
DD
DQL7
CK
CK
A10/AP
A15
A12/BC
A1
A11
A14
8
V
DDQ
DQU6
DQU2
V
SSQ
V
SSQ
DQL3
V
SS
DQL5
V
SS
V
DD
ZQ
V
REFCA
BA1
A4
A6
A8
9
V
SS
V
SSQ
V
DDQ
V
DD
V
DDQ
V
SSQ
V
SSQ
V
DDQ
NC
CKE
NC
V
SS
V
DD
V
SS
V
DD
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
A
2
3
4
5
6
7
8
9
Ball Locations (x16)
Populated ball
Ball not populated
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Top view
(See the balls through the package)
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Signal Pin Description
Pin
CK, CK
Type
Input
Function
Clock :
CK and CK are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to
the crossings of CK and CK
Clock Enable :
CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh oper-
ation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self
refresh exit. After V
REFCA
has become stable during the power on and initialization sequence, it must
be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout
read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-
down. Input buffers, excluding CKE, are disabled during Self -Refresh.
Chip Select :
All commands are masked when CS is registered HIGH. CS provides for external Rank
selection on systems with multiple Ranks. CS is considered part of the command code.
On Die Termination :
ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM. The ODT pin will be
ignored if the Mode Register (MR1) is programmed to disable ODT.
Command Inputs :
RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask :
DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
Bank Address Inputs :
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command
is being applied. Bank address also determines which mode register is to be accessed during a MRS
cycle.
Address Inputs :
Provided the row address for Active commands and the column address for Read /
Write commands to select one location out of the memory array in the respective bank. (A10/AP and
A12/BC have additional functions, see below)
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge :
A10 is sampled during Read/Write commands to determine whether Autoprecharge
should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge;
LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged,
the bank is selected by bank addresses.
Burst Chop :
A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly)
will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details.
Active Low Asynchronous Reset :
Reset is active when RESET is LOW, and inactive when RESET
is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
Data Input/ Output :
Bi-directional data bus.
Data Strobe :
Output with read data, input with write data. Edge-aligned with read data, centered in
write data. The data strobe DQS is paired with differential signals DQS, respectively, to provide differ-
ential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
No Connect: No internal electrical connection is present.
CKE
Input
CS
ODT
Input
Input
RAS, CAS, WE
DM
BA0 - BA2
Input
Input
Input
A0 - A15
Input
A10 / AP
Input
A12 / BC
RESET
Input
Input
DQ
DQSL, DQSL
DQSU, DQSU
Input/
Output
Input/
Output
NC
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AS4C512M16D3LA
Pin
VDDQ
VSSQ
VDD
VSS
VREFDQ
VREFCA
ZQ
Type
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Function
DQ power supply: 1.35V ,1.283V to 1.45V operational; compatible to 1.5V +/- 0.075V operation
DQ Ground
Power Supply: 1.35V ,1.283V to 1.45V operational; compatible to 1.5V +/- 0.075V operation
Ground
Reference Voltage for DQ
Reference Voltage for CA
Reference Pin for ZQ calibration
NOTE : Input only pins ( BA0-BA2, A0-A15, RAS, CAS, WE, CS, CKE, ODT and RESET ) do not supply termination.
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