GS4576C09/18/36L
144-Ball
BGA
Commercial Temp
Industrial Temp
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 16M x 36, 32M x 18, and 64M x 9 organizations available
• 8 banks
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (16K refresh for each bank; 128K refresh
command must be issued in total each 32 ms)
• 144-ball
BGA
package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60 matched impedance outputs
• 2.5 V V
EXT
, 1.8 V V
DD
, 1.5 V or 1.8 V V
DDQ
I/O
• On-die termination (ODT) R
TT
• Commerical and Industrial Temperature
Commercial (+0°
T
C
+95°C)
Industrial (–40°
T
C
+95°C)
64M x 9, 32M x 18, 16M x 36
576Mb CIO Low Latency DRAM (LLDRAM II)
Introduction
533 MHz–300 MHz
2.5 V V
EXT
1.8 V V
DD
1.5 V or 1.8 V V
DDQ
The GSI Technology 576Mb Low Latency DRAM
(LLDRAM II) is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V V
EXT
and 1.8 V V
DD
for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent
BGA
144-ball package.
Rev: 1.04 11/2013
1/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
64M x 9 Mb Ball Assignments—144-Ball
BGA—Top
View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
1
A21
A5
A8
B2
NF
2
DK
REF
WE
A18
A15
V
SS
V
TT
V
DD
V
REF
2
V
SS
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
A6
A9
NF
2
DK
CS
A16
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
ZQ
3
V
EXT
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
A7
V
SS
V
DD
V
DD
V
SS
A17
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
V
EXT
4
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
5
6
7
8
9
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
10
V
EXT
DQ0
DQ1
QK0
DQ2
DQ3
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
V
EXT
11
TMS
DNU
3
DNU
3
QK0
DNU
3
DNU
3
A1
A4
B0
B1
A14
A11
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
TDO
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.04 11/2013
2/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
32M x 18 Ball Assignments—144-Ball
BGA—Top
View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
1
A21
2
A5
A8
B2
NF
3
DK
REF
WE
A18
A15
V
SS
V
TT
V
DD
V
REF
2
V
SS
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
A6
A9
NF
3
DK
CS
A16
DNU
4
DNU
4
QK1
DNU
4
DNU
4
ZQ
3
V
EXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
V
SS
V
DD
V
DD
V
SS
A17
DQ14
DQ15
QK1
DQ16
DQ17
V
EXT
4
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
5
6
7
8
9
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
10
V
EXT
DQ0
DQ1
QK0
DQ2
DQ3
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
V
EXT
11
TMS
DNU
4
DNU
4
QK0
DNU
4
DNU
4
A1
A4
B0
B1
A14
A11
DNU
4
DNU
4
DNU
4
DNU
4
DNU
4
TDO
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address input signal. It may be connected to GND.
3. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
4. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
Rev: 1.04 11/2013
3/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
16M x 36 Ball Assignments—144-Ball
BGA—Top
View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
1
A21
2
A5
A8
B2
DK0
DK1
REF
WE
A18
A15
V
SS
V
TT
V
DD
V
REF
2
V
SS
DQ8
DQ10
DQ12
DQ14
DQ16
A6
A9
DK0
DK1
CS
A16
DQ24
DQ22
QK1
DQ20
DQ18
ZQ
3
V
EXT
DQ9
DQ11
DQ13
DQ15
DQ17
A7
V
SS
V
DD
V
DD
V
SS
A17
DQ25
DQ23
QK1
DQ21
DQ19
V
EXT
4
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
5
6
7
8
9
V
SS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
SS
10
V
EXT
DQ1
DQ3
QK0
DQ5
DQ7
A2
V
SS
V
DD
V
DD
V
SS
A12
DQ35
DQ33
DQ31
DQ29
DQ27
V
EXT
11
TMS
DQ0
DQ2
QK0
DQ4
DQ6
A1
A4
B0
B1
A14
A11
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
12
TCK
V
DD
V
TT
V
SS
A20
2
QVLD
A0
A3
CK
CK
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
Notes:
1. Reserved for future use. This pin may be connected to GND.
2. Reserved for future use. This pin may have parasitic characteristics of an address pin. It may be connected to GND.
Rev: 1.04 11/2013
4/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS4576C09/18/36L
Ball Descriptions
Symbol
A0–A21
BA0–B2
CK, CK
Type
Input
Input
Input
Input
Input
Description
Address Inputs—A0–A21
define the row and column addresses for Read and Write Operations. During
a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
Bank Address inputs—Select
to which internal bank a command is being applied.
Input Clock—CK
and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180º out of phase with CK.
Chip Select—CS
enables the command decoder when Low and disables it when High. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
Data Input—The
DQ signals form the 36-bit data bus. During Read commands, the data is referenced to
both edges of QKx. During Write commands, the data is sampled at both edges of DK.
Input Data Clock—DK
and DK are the differential input data clocks. All input data is referenced to both
edges of DK. DK is ideally 180º out of phase with DK. For the x36 device, DQ0– DQ17 are referenced to
DK0 and DK0 and DQ18–DQ35 are referenced to DK1 and DK1. For the x9 and x18 devices, all DQs
are referenced to DK and DK. All DKx and DKx pins must always be supplied to the device.
Input Data Mask—The
DM signal is the input mask signal for Write data. Input data is masked when DM
is sampled High. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
IEEE 1149.1 clock input—This
ball must be tied to V
SS
if the JTAG function is not used.
IEEE 1149.1 test inputs—These
balls may be left as no connects if the JTAG function is not used.
Command Inputs—Sampled
at the positive edge of CK, WE and REF define (together with CS) the
command to be executed.
Input Reference Voltage—Nominally
V
DDQ
/2. Provides a reference voltage for the input buffers.
External Impedance (25–60)—This
signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to V
DD
invokes the
Maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Output Data Clocks—QKx
and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of
phase with QKx. For the x36 device, QK0 and QK0 are aligned with DQ0–DQ17, and QK1 and QK1 are
aligned with DQ18–DQ35. For the x18 device, QK0 and QK0 are aligned with DQ0–DQ8, while QK1 and
QK1 are aligned with Q9–Q17. For the x9 device, all DQs are aligned with QK0 and QK0.
CS
DQ0–DQ35
DK, DK
Input
DM
Input
TCK
TMS, TDI
WE, REF
V
REF
Input
Input
Input
Input
ZQ
I/O
QKx, QKx
Output
Rev: 1.04 11/2013
5/62
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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