Datasheet> 器件分类 > 半导体> 存储器> MT40A4G4DVN-075H:E TR

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MT40A4G4DVN-075H:E TR: 产品描述SDRAM - DDR4 存储器 IC 16Gb（4G x 4）并联 1.33 GHz 27 ns 78-FBGA（7.5 x 11）; 产品类别半导体存储器; 文件大小3MB，共75页; 制造商Micron Technology; 官网地址http://www.mdtic.com.tw/; 标准

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MT40A4G4DVN-075H:E TR概述

SDRAM - DDR4 存储器 IC 16Gb（4G x 4）并联 1.33 GHz 27 ns 78-FBGA（7.5 x 11）

MT40A4G4DVN-075H:E TR规格参数

参数名称	属性值
类别
厂商名称	Micron Technology
包装	卷带（TR）
存储器类型	易失
存储器格式	DRAM
技术	SDRAM - DDR4
存储容量	16Gb（4G x 4）
存储器接口	并联
电压 - 供电	1.14V ~ 1.26V
工作温度	0°C ~ 95°C（TC）
安装类型	表面贴装型
封装/外壳	78-TFBGA
供应商器件封装	78-FBGA（7.5 x 11）
时钟频率	1.33 GHz
访问时间	27 ns
基本产品编号	MT40A4

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16Gb, 32Gb: x4, x8 3DS DDR4 SDRAM

Description

3-Dimensional Stack (3DS) DDR4 SDRAM

MT40A4G4, MT40A8G4, MT40A2G8, MT40A4G8

Description

The 16Gb, 2-high (2H) and 32Gb, 4-high (4H) 3-di-

mensional stack (3DS) DDR4 SDRAM use Micron’s

special 3DS 8Gb DDR4 SDRAM organized as two or

four logical ranks. Refer to Micron’s 8Gb DDR4

SDRAM data sheet for the specifications not included

in this document. Specifications for base part number

MT40A2G4 correspond to 2H 3DS manufacturing part

number MT40A4G4 and to 4H 3DS manufacturing

part number MT40A8G4; specifications for base part

number MT40A1G8 correspond to 2H 3DS manufac-

turing part number MT40A2G8 and to 4H 3DS manu-

facturing part number MT40A4G8.

Options

• 2H configurations

– 128 Meg x 4 x 16 banks x 2 ranks

– 64 Meg x 8 x 16 banks x 2 ranks

• 4H configurations

– 128 Meg x 4 x 16 banks x 4ranks

– 64 Meg x 8 x 16 banks x 4 ranks

• FBGA package (Pb-free)

– 2H 78-ball FBGA

(8.0mm x 12mm x 1.2mm) Die Rev :G

– 2H 78-ball FBGA

(7.5mm x 11mm x 1.2mm) Die Rev :E

– 4H 78-ball FBGA

(8.0mm x 12mm x 1.2mm) Die Rev :G

– 4H 78-ball FBGA

(7.5mm x 11mm x 1.2mm) Die Rev :E

• Timing – cycle time

– 0.625ns @ CL = 26 (DDR4-3200)

– 0.682ns @ CL = 24 (DDR4-2933)

– 0.750ns @ CL = 22 (DDR4-2666)

– 0.833ns @ CL = 19 (DDR4-2400)

– 0.833ns @ CL = 20 (DDR4-2400)

– 0.937ns @ CL = 18 (DDR4-2133)

• Self refresh

– Standard

• Operating temperature

– Commercial (0°C

≤

95°C)

• Revision

Notes:

Marking

4G4

2G8

8G4

4G8

HPR

DVN

KVA

CLU

-062H

-068H

-075H

-083J

-083H

-093H

None

:G, :E

Features

• Uses Micron 3DS 8Gb die

• Single electrical signal load for each command, ad-

dress and data pin

• Two or four logical ranks (includes one or two 2C

pins)

• Each rank has 4 groups of 4 internal banks for con-

current operation

• V

= V

DDQ

= 1.2V (1.14–1.26V)

• 1.2V V

DDQ

-terminated I/O

• JEDEC-standard ball-out

• Low-profile package

• T

of 0°C to 95°C

– 0°C to 85°C: 8192 refresh cycles in 64ms

– 85°C to 95°C: 8192 refresh cycles in 32ms

1. CL = CAS (READ) latency.

2. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on http://www.micron.com for

available offerings.

CCMTD-1725822587-10122

16gb_32gb_3ds.pdf - Rev. C 02/19 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16Gb, 32Gb: x4, x8 3DS DDR4 SDRAM

Description

Contents

Important Notes and Warnings ......................................................................................................................... 6

3DS (Master/Slave) Overview ............................................................................................................................ 7

Functionality .................................................................................................................................................... 8

Addressing ................................................................................................................................................. 10

All-Die Commands vs. Single-Die Commands ............................................................................................. 10

Initialization and Reset ................................................................................................................................... 11

Mode Register Set ........................................................................................................................................... 11

Unique 3DS MRS Values for Mode Register 1 ............................................................................................... 11

Multipurpose Register ................................................................................................................................ 12

Post Package Repair .................................................................................................................................... 12

Command/Address Parity ............................................................................................................................... 12

Calibration ..................................................................................................................................................... 13

ACTIVE Operation .......................................................................................................................................... 14

Column Access Operation (WRITE and READ) Timings .................................................................................... 16

READ Operation ............................................................................................................................................. 18

READ Operation Examples ......................................................................................................................... 18

WRITE Operations .......................................................................................................................................... 21

WRITE Operation Examples ........................................................................................................................ 21

PRECHARGE Commands ................................................................................................................................ 23

REFRESH Operation ....................................................................................................................................... 23

SELF REFRESH Operation ............................................................................................................................... 24

Power-Down Operations ................................................................................................................................. 25

On-Die Termination (ODT) ............................................................................................................................. 25

DRAM Package Electrical Specifications .......................................................................................................... 26

Speed Bin Tables ............................................................................................................................................ 29

Current Specifications – Measurement Conditions ........................................................................................... 46

, I

, and I

DDQ

Measurement Conditions ................................................................................................. 46

Definitions ........................................................................................................................................... 48

Current Specifications – Patterns and Test Conditions ...................................................................................... 51

Current Test Definitions and Patterns .......................................................................................................... 51

Specifications ....................................................................................................................................... 64

Current Specifications – Limits ........................................................................................................................ 65

Package Dimensions ....................................................................................................................................... 73

Thermal Characteristics .................................................................................................................................. 74

CCMTD-1725822587-10122

16gb_32gb_3ds.pdf - Rev. C 02/19 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16Gb, 32Gb: x4, x8 3DS DDR4 SDRAM

Description

List of Figures

Figure 1: 2-High 3DS Functional Block Diagram ............................................................................................... 8

Figure 2: 4-High 3DS Functional Block Diagram ............................................................................................... 9

Figure 3: CA Parity Error During Refresh ......................................................................................................... 13

Figure 4:

RRD and

FAW Timing Example ...................................................................................................... 14

Figure 5: READ BL8 to READ BL8 (

CCD = 4) Example ..................................................................................... 19

Figure 6: READ BL8 to READ BL8 (

CCD = 5) Example ..................................................................................... 19

Figure 7: READ BL8 to READ BL8 (

CCD = 6) Example ..................................................................................... 20

Figure 8: WRITE BL8 to WRITE BL8 (

CCD = 4) Example .................................................................................. 22

Figure 9: WRITE BL8 to WRITE BL8 (

CCD > 4) Example .................................................................................. 22

Figure 10: REFRESH-to-REFRESH Command Timing Example ....................................................................... 24

Figure 11: SELF REFRESH Command Timing Example ................................................................................... 25

Figure 12: Measurement Setup and Test Load for I

DDx

, I

PPx

and I

DDQx

.............................................................. 47

Figure 13: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ......................................... 47

Figure 14: 78-Ball FBGA Die Rev. G (package codes HPR and KVA) ................................................................... 73

Figure 15: Thermal Measurement Point ......................................................................................................... 74

CCMTD-1725822587-10122

16gb_32gb_3ds.pdf - Rev. C 02/19 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16Gb, 32Gb: x4, x8 3DS DDR4 SDRAM

Description

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 2

Table 2: 2H Addressing .................................................................................................................................... 2

Table 3: 4H Addressing .................................................................................................................................... 2

Table 4: 3DS Signals ...................................................................................................................................... 10

Table 5: 2H Stack Addressing ......................................................................................................................... 10

Table 6: 4H Stack Addressing ......................................................................................................................... 10

Table 7: Commands/Operations vs. Ranks Impacted ...................................................................................... 10

Table 8: Truth Table for MRS Commands ........................................................................................................ 11

Table 9: MR1 Register Definition .................................................................................................................... 12

Table 10: 3DS Device

RRD and

FAW Timing at 1600/1866/2133/2400 ............................................................. 14

Table 11: 3DS Device

RRD and

FAW Timing at 2666/2933/3200 ..................................................................... 15

Table 12: Minimum Column-to-Column Timing for 2-High and 4-High Stacks at 1600/1866/2133/2400/2666 ... 16

Table 13: Minimum Column-to-Column Timing for 2-High and 4-High Stacks at 2933/3200 ............................ 17

Table 14: Refresh Timing Parameters .............................................................................................................. 23

Table 15: Allowable SELF REFRESH Commands ............................................................................................. 24

Table 16: DRAM Provisional Package Electrical Specifications for x4 and x8 3DS Devices .................................. 26

Table 17: Pad Input/Output Provisional Capacitance for x4 and x8 3DS Devices ............................................... 28

Table 18: DDR4-1600 3DS Speed Bins and Operating Conditions ..................................................................... 30

Table 19: DDR4-1866 3DS Speed Bins and Operating Conditions ..................................................................... 32

Table 20: DDR4-2133 3DS Speed Bins and Operating Conditions ..................................................................... 34

Table 21: DDR4-2400 3DS Speed Bins and Operating Conditions ..................................................................... 36

Table 22: DDR4-2666 3DS Speed Bins and Operating Conditions ..................................................................... 38

Table 23: DDR4-2933 3DS Speed Bins and Operating Conditions ..................................................................... 40

Table 24: DDR4-3200 3DS Speed Bins and Operating Conditions ..................................................................... 43

Table 25: Basic I

, I

and I

DDQ

Measurement Conditions ............................................................................. 48

Table 26: I

DD0

and I

PP0

Measurement-Loop Pattern

....................................................................................... 51

Table 27: I

DD1

Measurement-Loop Pattern

.................................................................................................... 52

Table 28: I

DD2N

, I

DD3N

and I

PP3P

Measurement-Loop Pattern

.......................................................................... 54

Table 29: I

DD2NT

Measurement-Loop Pattern

................................................................................................ 55

Table 30: I

DD4R

Measurement-Loop Pattern

.................................................................................................. 56

Table 31: I

DD4W

Measurement-Loop Pattern

.................................................................................................. 57

Table 32: I

DD4Wc

Measurement-Loop Pattern

................................................................................................ 58

Table 33: I

DD5B1

Measurement-Loop Pattern

................................................................................................. 59

Table 34: I

DD5B2

Measurement-Loop Pattern

................................................................................................. 61

Table 35: I

DD7

Measurement-Loop Pattern

.................................................................................................... 63

Table 36: Timings used for I

, I

, and I

DDQ

Measurement – Loop Patterns .................................................... 64

Table 37: 2-High I

, I

and I

DDQ

Current Limits; Die Rev. G (0°

≤

85°C) ................................................... 65

Table 38: 4-High I

, I

and I

DDQ

Current Limits; Die Rev. G (0°

≤

85°C) ................................................... 66

Table 39: 2-High I

, I

and I

DDQ

Current Limits; Die Rev. E (0°

≤

85°C) ................................................... 68

Table 40: 4-High I

, I

and I

DDQ

Current Limits; Die Rev. E (0°

≤

85°C) ................................................... 70

Table 41: Thermal Characteristics .................................................................................................................. 74

CCMTD-1725822587-10122

16gb_32gb_3ds.pdf - Rev. C 02/19 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT40A4G4DVN-075H:E TR

MT40A4G4DVN-075H:E TR概述

MT40A4G4DVN-075H:E TR规格参数

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