Features
•
Single Voltage Operation Read/Write: 2.65V - 3.6V
•
Access Time – 70 ns
•
Sector Erase Architecture
– One Hundred Twenty-seven 32K Word (64K Bytes) Main Sectors with
Individual Write Lockout
– Eight 4K Word (8K Bytes) Sectors with Individual Write Lockout
Fast Word Program Time – 10 µs
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 100 ms
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending
Erase of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 10 mA Active
– 15 µA Standby
VPP Pin for Write Protection and Accelerated Program Operation
WP Pin for Sector Protection
RESET Input for Device Initialization
Flexible Sector Protection
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Minimum 100,000 Erase Cycles
Common Flash Interface (CFI)
Green (Pb/Halide-free/RoHS Compliant) Packaging
•
•
•
•
64-megabit
(4M x 16)
3-volt Only
Flash Memory
AT49BV640D
AT49BV640DT
•
•
•
•
•
•
•
•
•
1. Description
The AT49BV640D(T) is a 2.7-volt 64-megabit Flash memory organized as 4,194,304
words of 16 bits each. The memory is divided into 135 sectors for erase operations.
The device is offered in a 48-ball CBGA package. The device has CE and OE control
signals to avoid any bus contention. This device can be read or reprogrammed using
a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place
the device in other operation modes such as program and erase. The device has
the capability to protect the data in any sector (see
“Flexible Sector Protection” on
page 6).
To increase the flexibility of the device, it contains an Erase Suspend and Program
Suspend feature. This feature will put the erase or program on hold for any amount of
time and let the user read data from or program data to any of the remaining sectors
within the memory.
The VPP pin provides data protection. When the V
PP
input is below 0.4V, the program
and erase functions are inhibited. When V
PP
is at 1.65V or above, normal program
and erase operations can be performed. With V
PP
at 10.0V, the program (Dual-word
Program command) operation is accelerated.
3608C–FLASH–11/06
2. Pin Configurations
Pin Name
A0 - A21
CE
OE
WE
RESET
VPP
I/O0 - I/O15
NC
VCCQ
WP
Pin Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Write Protection and Power Supply for Accelerated Program Operations
Data Inputs/Outputs
No Connect
Output Power Supply
Write Protect
2.1
48-ball CBGA – Top View
1
A
A13
A11
A10
A12
A8
VPP
WP
A19
A17
A6
I/O8
I/O9
A7
A5
A3
CE
I/O0
A4
A2
A1
A0
GND
OE
2
3
4
5
6
7
8
B
A14
WE RESET A18
A9
A21
A20
C
A15
D
A16 I/O14 I/O5 I/O11 I/O2
E
VCCQ I/O15 I/O6 I/O12 I/O3
F
GND
I/O7 I/O13 I/O4
VCC I/O10 I/O1
2
AT49BV640D(T)
3608C–FLASH–11/06
AT49BV640D(T)
3. Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
A0 - A21
INPUT
BUFFER
DATA
REGISTER
IDENTIFIER
REGISTER
STATUS
REGISTER
COMMAND
REGISTER
ADDRESS
LATCH
DATA
COMPARATOR
CE
WE
OE
RESET
WP
WRITE
STATE
MACHINE
Y-DECODER
Y-GATING
PROGRAM/ERASE
VOLTAGE
SWITCH
VPP
VCC
GND
X-DECODER
MAIN
MEMORY
4. Device Operation
4.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are
used to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. The address is latched
on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or
the CE pulse, whichever occurs first. The addresses used in the command sequences are not
affected by entering the command sequences.
4.2
Read
The AT49BV640D(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the
outputs. The outputs are put in the high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus contention.
3
3608C–FLASH–11/06
4.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET pin halts the
present device operation and puts the outputs of the device in a high-impedance state. When
a high level is reasserted on the RESET pin, the device returns to read mode.
4.4
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is
a logical “1”. The individual sectors can be erased by using the Sector Erase command.
4.4.1
Sector Erase
The device is organized into 135 sectors (SA0 - SA134) that can be individually erased. The
Sector Erase command is a two-bus cycle operation. The sector address and the D0H Data
Input command are latched on the rising edge of WE. The sector erase starts after the rising
edge of WE of the second cycle provided the given sector has not been protected. The erase
operation is internally controlled; it will automatically time to completion. The maximum time to
erase a sector is t
SEC
. An attempt to erase a sector that has been protected will result in the
operation terminating immediately.
4.5
Word Programming
Once a memory sector is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the Internal Device command register and is a two-bus
cycle operation. The device will automatically generate the required internal program pulses.
Any commands except Read Status Register, Program Suspend and Program Resume writ-
ten to the chip during the embedded programming cycle will be ignored. If a hardware reset
happens during programming, the data at the location being programmed will be corrupted.
Please note that a data “0” cannot be programmed back to a “1”; only erase operations can
convert “0”s to “1”s. Programming is completed after the specified t
BP
cycle time. If the pro-
gram status bit is a “1”, the device was not able to verify that the program operation was
performed successfully. The status register indicates the programming status. While the pro-
gram sequence executes, status bit I/O7 is “0”.
4.6
VPP Pin
The circuitry of the AT49BV640D(T) is designed so that the device cannot be programmed or
erased if the V
PP
voltage is less that 0.4V. When V
PP
is at 1.65V or above, normal program
and erase operations can be performed. The VPP pin cannot be left floating.
4
AT49BV640D(T)
3608C–FLASH–11/06
AT49BV640D(T)
4.7
Read Status Register
The status register indicates the status of device operations and the success/failure of that
operation. The Read Status Register command causes subsequent reads to output data from
the status register until another command is issued. To return to reading from the memory,
issue a Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status
read, or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing
the preferred operation (see
Table 4-1).
Table 4-1.
WSMS
7
Status Register Bit Definition
ESS
6
ES
5
PRS
4
VPPS
3
PSS
2
Notes
SLS
1
R
0
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 = SECTOR LOCK STATUS (SLS)
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
SR0 = Reserved for Future Enhancements (R)
Note:
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
When this bit is set to “1”, WSM has attempted but failed to
program a word
The V
PP
status bit does not provide continuous indication of VPP
level. The WSM interrogates V
PP
level only after the Program or
Erase command sequences have been entered and informs the
system if V
PP
has not been switched on. The V
PP
is also checked
before the operation is verified by the WSM.
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
This bit is reserved for future use and should be masked out
when polling the status register.
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
5
3608C–FLASH–11/06
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
