Numonyx
®
Axcell™ P30-65nm Flash Memory
128-Mbit, 64-Mbit Single Bit per Cell (SBC)
Datasheet
Product Features
High Performance:
— 65ns initial access time for Easy BGA and
QUAD+
— 75ns initial access time for TSOP
— 25ns 8-word asynchronous-page read mode
— 52MHz with zero WAIT states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16- and continuous-word options for
burst mode
— 1.8V Low Power buffered programming at
1.8MByte/s
(Typ) using 256-word buffer
— Buffered Enhanced Factory Programming at
3.2MByte/s (typ) using 256-word buffer
Enhanced Security:
—
—
—
—
—
—
Absolute write protection: VPP = Vss
Power-transition erase/program lockout
Individual zero-latency block locking
Individual block lock-down capability
Password Access feature
One-Time Programmable Register:
— 64 OTP bits, programmed with unique
information by Numonyx
— 2112 OTP bits, available for customer
programming
Software:
—
20µs
(Typ) program suspend
—
20µs
(Typ) erase suspend
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
Architecture:
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
— 128-KByte array blocks
— Blank Check to verify an erased block
Density and Packaging:
—
—
—
—
—
—
—
—
56-Lead TSOP (128-Mbit, 64-Mbit)
64-Ball Easy BGA (128-Mbit, 64-Mbit)
88-Ball QUAD+ Package (128-Mbit)
16-bit wide data bus
JESD47E Compliant
Operating temperature: –40°C to +85°C
Minimum 100,000 erase cycles
65nm process technology
Voltage and Power:
—
—
—
—
VCC (core) voltage: 1.7V – 2.0V
VCCQ (I/O) voltage: 1.7V – 3.6V
Standby current: 30µA(Typ)/55µA(Max)
Continuous synchronous read current: 23mA
(Typ)/28mA (Max) at 52MHz
Quality and Reliability:
Datasheet
1
Apr 2010
Order Number: 208033-02
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and Axcell are trademarks or registered trademarks of Numonyx , B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Apr 2010
Order Number: 208033-02
P30-65nm SBC
Contents
1.0
Functional Description
............................................................................................... 5
1.1
Introduction ....................................................................................................... 5
1.2
Overview ........................................................................................................... 5
1.3
Memory Map....................................................................................................... 6
Package Information
................................................................................................. 7
2.1
56-Lead TSOP..................................................................................................... 7
2.2
64-Ball Easy BGA Package .................................................................................... 8
2.3
QUAD+ SCSP Packages ...................................................................................... 10
Pinouts/Ballouts
..................................................................................................... 11
Signals
.................................................................................................................... 14
Bus Operations
........................................................................................................ 16
5.1
Read - Asynchronous Mode................................................................................. 16
5.2
Read - Synchronous Mode .................................................................................. 16
5.3
Write ............................................................................................................... 17
5.4
Output Disable .................................................................................................. 17
5.5
Standby ........................................................................................................... 17
5.6
Reset............................................................................................................... 18
Command Set
.......................................................................................................... 19
6.1
Device Command Codes ..................................................................................... 19
6.2
Device Command Bus Cycles .............................................................................. 20
Read
7.1
7.2
7.3
7.4
7.5
Operation........................................................................................................
22
Read Array ....................................................................................................... 22
Read Device Identifier........................................................................................ 22
Read CFI .......................................................................................................... 23
Read Status Register ......................................................................................... 23
Clear Status Register ......................................................................................... 23
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Program Operation
.................................................................................................. 24
8.1
Word Programming ........................................................................................... 24
8.2
Buffered Programming ....................................................................................... 24
8.3
Buffered Enhanced Factory Programming.............................................................. 25
8.4
Program Suspend .............................................................................................. 27
8.5
Program Resume............................................................................................... 28
8.6
Program Protection............................................................................................ 28
Erase Operation.......................................................................................................
29
9.1
Block Erase ...................................................................................................... 29
9.2
Blank Check ..................................................................................................... 29
9.3
Erase Suspend .................................................................................................. 30
9.4
Erase Resume................................................................................................... 30
9.5
Erase Protection ................................................................................................ 30
9.0
10.0 Security
................................................................................................................... 31
10.1 Block Locking.................................................................................................... 31
10.2 Selectable OTP Blocks ........................................................................................ 33
10.3 Password Access ............................................................................................... 33
11.0 Register...................................................................................................................
34
11.1 Status Register (SR) .......................................................................................... 34
11.2 Read Configuration Register (RCR) ...................................................................... 34
Datasheet
3
Apr 2010
Order Number: 208033-02
P30-65nm SBC
11.3
One-Time Programmable (OTP) Registers .............................................................40
12.0 Power and Reset Specifications
...............................................................................43
12.1 Power-Up and Power-Down .................................................................................43
12.2 Reset Specifications ...........................................................................................43
12.3 Power Supply Decoupling....................................................................................44
13.0 Maximum Ratings and Operating Conditions
............................................................45
13.1 Absolute Maximum Ratings .................................................................................45
13.2 Operating Conditions..........................................................................................45
14.0 Electrical Specifications
...........................................................................................46
14.1 DC Current Characteristics ..................................................................................46
14.2 DC Voltage Characteristics ..................................................................................47
15.0 AC Characteristics
....................................................................................................48
15.1 AC Test Conditions.............................................................................................48
15.2 Capacitance ......................................................................................................49
15.3 AC Read Specifications ......................................................................................50
15.4 AC Write Specifications .......................................................................................54
15.5 Program and Erase Characteristics .......................................................................58
16.0 Ordering Information...............................................................................................59
A
Supplemental Reference Information.......................................................................61
A.1
Common Flash Interface .....................................................................................61
A.2
Flowcharts ........................................................................................................73
A.3
Write State Machine ...........................................................................................83
Conventions - Additional Documentation
.................................................................87
B.1
Acronyms .........................................................................................................87
B.2
Definitions and Terms ........................................................................................87
Revision History.......................................................................................................89
B
C
Datasheet
4
Apr 2010
Order Number: 208033-02
P30-65nm SBC
1.0
1.1
Functional Description
Introduction
This document provides information about the Numonyx
®
Axcell
TM
P30-65nm Single Bit
per Cell (SBC) Flash memory and describes its features, operations, and specifications.
P30-65nm SBC device is offered in 64-Mbit and 128-Mbit. Benefits include high-speed
interface NOR device, and support for code and data storage. Features include high-
performance synchronous-burst read mode, a dramatical improvement in buffer
program time through larger buffer size, fast asynchronous access times, low power,
flexible security options, and three industry-standard package choices.
P30-65nm SBC device is manufactured using 65nm process technology.
1.2
Overview
P30-65nm SBC device provides high performance on a 16-bit data bus. Individually
erasable memory blocks are sized for optimum code and data storage. Upon initial
power-up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register (RCR) enables synchronous burst-mode
reads. In synchronous burst mode, output data is synchronized with a user-supplied
clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast buffer program and erase operations. The device features
a 256-word buffer to enable optimum programming performance, which can improve
system programming throughput time significantly to
1.8MByte/s.
Designed for low-voltage systems, the P30-65nm SBC device supports read operations
with VCC at 1.8V, and erase and program operations with VPP at 1.8V or 9.0V. Buffered
Enhanced Factory Programming provides the fastest flash array programming
performance with VPP at 9.0V, which increases factory throughput with 3.2Mbyte/s.
With VPP at 1.8V, VCC and VPP can be tied together for a simple, ultra low power
design. In addition to voltage flexibility, a dedicated VPP connection provides complete
data protection when VPP
≤
V
PPLK
.
The Command User Interface is the interface between the system processor and all
internal operations of the device. An internal Write State Machine automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
A device command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations.
The OTP Register allows unique flash device identification that can be used to increase
system security. The individual Block Lock feature provides zero-latency block locking
and unlocking. The P30-65nm SBC device adds enhanced protection via Password
Access; this new feature allows write and/or read access protection of user-defined
blocks. In addition, the P30-65nm SBC device also has backward-compatible One-Time
Programmable (OTP) permanent block locking security feature.
Datasheet
5
Apr 2010
Order Number:208033-02
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