Features
•
Low-voltage Operation
•
•
•
•
•
•
•
•
•
•
•
– 2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 131,072 x 8
2-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400 kHz (2.7V) and 1 MHz (5V) Clock Rate
Write Protect Pin for Hardware and Software Data Protection
256-byte Page Write Mode (Partial Page Writes Allowed)
Random and Sequential Read Modes
Self-timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 100,000 Write Cycles/Page
– Data Retention: 40 Years
8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA
TM
Packages
2-wire Serial
EEPROM
1M (131,072 x 8)
Description
The AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The devices are available in space-
saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA
packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.
AT24C1024
8-lead PDIP
Pin Configurations
Pin Name
A1
SDA
SCL
WP
NC
Function
Address Input
Serial Data
Serial Clock Input
Write Protect
No Connect
NC
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead Leadless Array
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
NC
A1
NC
GND
8-lead SOIC
NC
A1
NC
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Bottom View
8-ball dBGA
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
NC
A1
NC
GND
Rev. 1471I–SEEPR–7/03
Bottom View
1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Block Diagram
2
AT24C1024
1471I–SEEPR–7/03
AT24C1024
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A1):
The A1 pin is a device address input that can be hard-
wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1
pin is hardwired, as many as two 1024K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). When the pin
is not hardwired, the default A1 is zero.
WRITE PROTECT (WP):
The hardware Write Protect pin is useful for protecting the entire
contents of the memory from inadvertent write operations. The write-protect input, when tied to
GND, allows normal write operations. When WP is tied high to V
CC
, all write operations to the
memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP
to V
CC
prior to a write operation creates a software write-protect function.
Memory
Organization
AT24C1024, 1024K SERIAL EEPROM:
The 1024K is internally organized as 512 pages of
256 bytes each. Random word addressing requires a 17-bit data word address.
3
1471I–SEEPR–7/03
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +2.7V.
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
1
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from: T
AI
= -40°C to +85°C, V
CC
= +2.7V to +5.5V, T
AC
= 0°C to +70°C,
V
CC
= +2.7V to +5.5V (unless otherwise noted).
Symbol
V
CC
I
CC
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
V
CC
= 3.0V
I
OL
= 2.1 mA
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
-0.6
V
CC
x 0.7
0.10
0.05
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
Test Condition
Min
2.7
Typ
Max
5.5
2.0
5.0
3.0
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
V
mA
mA
µA
µA
µA
µA
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
4
AT24C1024
1471I–SEEPR–7/03
AT24C1024
AC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +85°C, V
CC
= +2.7V to +5.5V, C
L
= 100 pF (unless
otherwise noted). Test conditions are listed in Note 2.
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
100K
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
0.25
0.6
50
10
Test Conditions
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
2.7V
≤
V
CC
≤
5.5V
0.4
1.3
0.4
0.6
0.05
0.05
0.5
1.3
0.25
0.6
0.25
0.6
0
100
0.3
100
300
0.55
0.9
Min
Max
1000
400
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write Cycles
Endurance
(1)
5.0V, 25°C, Page Mode
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 kΩ (2.7V, 5V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤50
ns
Input and output timing reference voltages: 0.5 V
CC
5
1471I–SEEPR–7/03
FPGA/CPLD
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