PIC24FJ64GP205/GU205 Family
16-Bit eXtreme Low-Power Microcontrollers with USB in
Low Pin Count Packages
High-Performance CPU
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Modified Harvard Architecture
64 Kbytes of Flash Memory
8 Kbytes of SRAM
Up to 16 MIPS Operation @ 32 MHz
8 MHz Fast RC (FRC) Internal Oscillator:
– 96 MHz PLL option
– Multiple clock divide options
– Fast start-up
17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16-Bit x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
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Universal Serial Bus (USB) Features
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USB v2.0 On-The-Go (OTG)
Dual Role Capable – Can Act as either Host or Device
Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode
Full-Speed USB Operation in Device mode
High-Precision PLL for USB
USB Device mode Operation from FRC Oscillator – No Crystal Oscillator Required
Supports Up to 32 Endpoints (16 bidirectional):
– USB module can use any RAM location on the device as USB endpoint buffers
On-Chip USB Transceiver with Interface for Off-Chip USB Transceiver
Supports Control, Interrupt, Isochronous and Bulk Transfers
On-Chip Pull-up and Pull-Down Resistors
Analog Features
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Up to 14-Channel, Software-Selectable 10/12-Bit Analog-to-Digital Converter:
– 12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
– 10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
– Sleep mode operation
– Low-voltage boost for input
– Band gap reference input feature
– Core-independent windowed threshold compare feature
©
2020 Microchip Technology Inc.
Advance Information Datasheet
DS30010221C-page 1
PIC24FJ64GP205/GU205 Family
– Auto-scan feature
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Three Analog Comparators with Input Multiplexing:
– Programmable reference voltage for comparators
eXtreme Low-Power Features
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Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast
Wake-up
Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
Retention Sleep with On-Chip Ultra Low-Power Retention Regulator
Functional Safety and Security Peripherals
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Fail-Safe Clock Monitor Operation:
– Detects clock failure and switches to on-chip, low-power RC Oscillator
Power-on Reset (POR), Brown-out Reset (BOR)
Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Programmable High/Low-Voltage Detect (HLVD)
Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
Deadman Timer (DMT) for Safety-Critical Applications
Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
Flash OTP by ICSP
™
Write Inhibit
CodeGuard
™
Security
ECC Flash Memory (64 Kbytes) with Fault Injection:
– Single Error Correction (SEC)
– Double-Error Detection (DED)
Customer OTP Memory
Unique Device Identifier (UDID)
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Special Microcontroller Features
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Supply Voltage Range of 2.0V to 3.6V
Operating Ambient Temperature Range of -40°C to +125°C
On-Chip Voltage Regulators (1.8V) for Low-Power Operation
ECC Flash Memory (64 Kbytes):
– 10,000 erase/write cycle endurance, typical
– Data retention: 20 years minimum
– Self-programmable under software control
– Flash OTP emulation
8-Kbyte SRAM
Programmable Reference Clock Output
In-Circuit Serial Programming
™
(ICSP
™
) and
In-Circuit Emulation (ICE) via Two Pins
JTAG Boundary Scan Support
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©
2020 Microchip Technology Inc.
Advance Information Datasheet
DS30010221C-page 2
PIC24FJ64GP205/GU205 Family
Peripheral Features
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High-Current Sink/Source 18 mA/18 mA on all I/O Pins
Independent, Low-Power 32 kHz Timer Oscillator
Two-Channel DMA Controller:
– Minimizes CPU overhead and increases data throughput
Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
Timer2/3: 16-Bit Timer/Counter, can Create 32-Bit Timer; Timer3 can Provide an A/D Trigger
Five MCCP modules, Each with a Dedicated 16/32-Bit Timer:
– Five 2-output MCCP modules
Two Variable Width, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes:
– Three-wire SPI (supports all four SPI modes)
– Up to 32-byte deep FIFO buffer
– I
2
S mode
– Speed up to 25 MHz
Two I
2
C Host and Client w/Address Masking, PMBus
™
and IPMI Support
Two UART modules:
– LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect, Break character support)
– RS-232 and RS-485 support
– IrDA
®
mode (hardware encoder/decoder functions)
Five External Interrupt Pins
Hardware Real-Time Clock and Calendar (RTCC)
Peripheral Pin Select (PPS) Allows Independent I/O Mapping of Many Peripherals
Configurable Interrupt-on-Change on All I/O Pins:
– Each pin is independently configurable for rising edge or falling edge change detection
Reference Clock Output with Programmable Divider
Four Configurable Logic Cell (CLC) Blocks:
– Two inputs and one output, all mappable to peripherals or I/O pins
– AND/OR/XOR logic and D/JK flip-flop functions
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PIC24FJ64GP205/GU205 Product Families
The device names, pin counts, memory sizes and peripheral availability of each device are listed in
Table 1.
The
following pages show their pinout diagrams.
©
2020 Microchip Technology Inc.
Advance Information Datasheet
DS30010221C-page 3
©
2020 Microchip Technology Inc.
Advance Information Datasheet
DS30010221C-page 4
Table 1. PIC24FJ64GP205/GU205 Family
Device
Program
Memory
(Kbytes)
SRAM Memory
(Kbytes)
Pins
I/O
PPS
DMA
10/12-Bit A/D
Channels
Comparators
CRC
MCCP (Two-
Output)
16-Bit Timers
I2C
SPI
LIN-UART/
®
IrDA
CLC
RTCC
USB OTG
JTAG BS
rotatethispage90
USB Devices
PIC24FJ64GU205
PIC24FJ64GU203
PIC24FJ64GU202
PIC24FJ32GU205
PIC24FJ32GU203
PIC24FJ32GU202
Non-USB Devices
PIC24FJ64GP205
PIC24FJ64GP203
PIC24FJ64GP202
PIC24FJ32GP205
PIC24FJ32GP203
PIC24FJ32GP202
64
64
64
32
32
32
8
8
8
8
8
8
48
36
28
48
36
28
39
27
21
39
27
21
29/33
24/24
18/18
29/33
24/24
18/18
2
2
2
2
2
2
14
14
10
14
14
10
3
3
3
3
3
3
Yes
Yes
Yes
Yes
Yes
Yes
5
5
5
5
5
5
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Yes
64
64
64
32
32
32
8
8
8
8
8
8
48
36
28
48
36
28
38
26
20
38
26
20
27/31
22/22
16/16
27/31
22/22
16/16
2
2
2
2
2
2
13
13
9
13
13
9
3
3
3
3
3
3
Yes
Yes
Yes
Yes
Yes
Yes
5
5
5
5
5
5
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC24FJ64GP205/GU205 Family
Yes
Yes
Yes
PIC24FJ64GP205/GU205 Family
Pin Diagrams
28-Pin QFN, UQFN
(1)
Note:
1.
Shaded
pins are up to 5.5 V
DC
tolerant.
Table 2. PIC24FJXXGP202 QFN, UQFN
(1)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
(1)
PGED1/AN2/LVDIN/C2INB/RP0/RB0
PGEC1/AN1-/AN3/C2INA/RP1/RB1
AN4/C1INB/RP2/SDA2/RB2
AN5/C1INA/RP3/SCL2/RB3
V
SS
OSCI/CLKI/C1IND/RA2
OSCO/CLKO/C2IND/RA3
SOSCI/C2IND/RP4/RB4
SOSCO/SCLKI/C2INC/PWRLCLK/RA4
V
DD
PGED3/RP5/ASDA1/RB5
PGEC3/RP6/ASCL1/RB6
RP7/INT0/RB7
TCK/RP8/SCL1
(2)
/RB8
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
(1)
TDO/C1INC/C2INC/C3INC/RP9/SDA1
(2)
/T1CK/RB9
V
SS
V
CAP
PGED2/TDI/RP10/ RB10
PGEC2/TMS/RP11/ RB11
AN8/LVDIN/RP12/RB12
AN7/C1INC/RP13/ RB13
CV
REF
/AN6/C3INB/RP14/RB14
AN9/C3INA/RP15/RB15
AV
SS
/V
SS
AV
DD
/V
DD
MCLR
V
REF
+/CV
REF
+/AN0/C3INC/RP26/ RA0
CV
REF
-/AN1/C3IND/RP27/RA1
Notes:
1.
RPn
and
RPIn
represent remappable pins for Peripheral Pin Select (PPS) functions.
2. Alternate pin assignments for I2C1 as determined by the I2C1SEL Configuration bit.
©
2020 Microchip Technology Inc.
Advance Information Datasheet
DS30010221C-page 5
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