Features
•
Minimal External Circuitry Requirements, no RF Components on the PC Board Except
•
•
•
•
•
•
•
•
•
•
•
•
Matching to the Receiver Antenna
High Sensitivity, Especially at Low Data Rates
SSO20 and SO20 package
Fully Integrated VCO
Supply Voltage 4.5V to 5.5V, Operating Temperature Range –40°C to
+105°C
Single-ended RF Input for Easy Adaptation to l/4 Antenna or Printed
Antenna on PCB
Low-cost Solution Due to High Integration Level
Various Types of Protocols Supported (i.e., PWM, Manchester and
Bi-phase)
Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal
Strength Indicator)
ESD Protection According to MIL-STD. 883 (4KV HBM)
High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW
Front-end Filter, up to 40 dB is thereby Achievable with Newer SAWs
Power Management (Polling) is Possible by Means of a Separate Pin via the
Microcontroller
Receiving Bandwidth BIF = 600 kHz
UHF ASK
Receiver
ATA5744
1. Description
The ATA5744 is a PLL receiver device for the receiving range of f
0
= 300 MHz to
450 MHz. It is developed for the demands of RF low-cost data communication sys-
tems with low data rates and fits for most types of modulation schemes including
Manchester, Bi-phase and most PWM protocols. Its main applications are in the areas
of telemetering, security technology and keyless-entry systems.
Figure 1-1.
1 Li cell
System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK
Remote control receiver
U2741B
Encoder
ATARx9x
XTO
ATA5744
Demod.
PLL
IF Amp
Data
interface
1...3
Micro-
controller
Keys
Antenna Antenna
VCO
PLL
XTO
Power
amp.
LNA
VCO
Rev. 4893A–RKE–11/05
2. Pin Configuration
Figure 2-1.
Pinning SO20 and SSO20
ENABLE
DVCC
LFGND
MODE
DATA
RSSI
XTO
LFVCC
NC
10
11
TEST
19
20
18
16
15
14
13
17
ATA5744
8
2
4
6
1
3
BR_0
BR_1
AVCC
5
MIXVCC
AGND
7
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
BR_0
BR_1
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
LFVCC
LF
LFGND
XTO
DVCC
MODE
RSSI
TEST
ENABLE
DATA
Function
Baud rate select LSB
Baud rate select MSB
Lower cut-off frequency data filter
Analog power supply
Analog ground
Digital ground
Power supply mixer
High-frequency ground LNA and mixer
RF input
Not connected
Power supply VCO
Loop filter
Ground VCO
Crystal oscillator
Digital power supply
Selecting 433.92 MHz /315 MHz
Low: 315 MHz (USA)
High: 433.92 MHz (Europe)
Output of the RSSI amplifier
Test pin, during operation at GND
Selecting operation mode
Low: sleep mode
High: receiving mode
Data output
2
ATA5744
4893A–RKE–11/05
LNAGND
LNA_IN
DGND
CDEM
9
12
LF
ATA5744
Figure 2-2.
Block Diagram
BR_0
BR_1
CDEM
ASK-
Demodulator
and data filter
RSSI
Dem_out
Data interface
DATA
RSSI
AVCC
RSSI IF Amp
Test
TEST
AGND
DGND
4. Order
MODE
DVCC
ENABLE
LFGND
Standby logic
LFVCC
IF Amp
MIXVCC
LPF
3 MHz
LNAGND
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LNA
64
LF
3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal into
a 1-MHz IF signal. According to
Figure 2-2,
the front end consists of an LNA (Low-Noise Ampli-
fier), LO (Local Oscillator), a mixer and RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency f
XTO
. The VCO (Voltage-Controlled Oscillator) gen-
erates the drive voltage frequency f
LO
for the mixer. f
LO
is dependent on the voltage at pin LF. f
LO
is divided by factor 64. The divided frequency is compared to f
XTO
by the phase frequency detec-
tor. The current output of the phase frequency detector is connected to a passive loop filter and
thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is
controlled in a way that f
LO
/64 is equal to f
XTO
. If f
LO
is determined, f
XTO
can be calculated using
the following formula:
f
XTO
= f
LO
/64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal.
According to
Figure 3-1,
the crystal should be connected to GND via a capacitor CL. The value
of that capacitor is recommended by the crystal supplier. The value of CL should be optimized
for the individual board layout to achieve the exact value of f
XTO
and hereby of f
LO
. When design-
ing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be
considered.
3
4893A–RKE–11/05
Figure 3-1.
PLL Peripherals
V
S
DVCC
C
L
XTO
LFGND
LF
V
S
R1
C9
C10
R1 = 820
Ω
C9 = 4.7 nF
C10 = 1 nF
LFVCC
The passive loop filter connected to pin LF is designed for a loop bandwidth of B
Loop
= 100 kHz.
This value for B
Loop
exhibits the best possible noise performance of the LO.
Figure 3-1
shows
the appropriate loop filter components to achieve the desired loop bandwidth
f
LO
is determined by the RF input frequency f
RF
and the IF frequency f
IF
using the following
formula:
f
LO
= f
RF
– f
IF
To determine f
LO
, the construction of the IF filter must be considered at this point. The nominal IF
frequency is f
IF
= 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter
is tuned by the crystal frequency f
XTO
. This means that there is a fixed relation between f
IF
and
f
LO
that depends on the logic level at pin mode. This is described by the following formulas:
MODE = 0 USA f
IF
= f
LO
/314
MODE = 1 Europe f
IF
= f
LO
/432.92
The relation is designed to achieve the nominal IF frequency of f
IF
= 1 MHz for most applica-
tions. For applications where f
RF
= 315 MHz, MODE must be set to '0'. In the case of
f
RF
= 433.92 MHz, MODE must be set to '1'. For other RF frequencies, f
IF
is not equal to 1 MHz.
f
IF
is then dependent on the logical level at pin MODE and on f
RF
.
Table 3-1 on page 5
summa-
rizes the different conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The para-
sitic board inductances and capacitances also influence the input matching. The RF receiver
ATA5744 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise
matching is the best choice for designing the transformation network.
A good practice when designing the network, is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best sensitivity.
If a SAW is implemented into the input network a mirror frequency suppression of
∆P
Ref
= 40 dB
can be achieved. There are SAWs available that exhibit a notch at
∆f
= 2 MHz. These SAWs
work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also
improved by using a SAW. In typical automotive applications, a SAW is used.
4
ATA5744
4893A–RKE–11/05
ATA5744
Figure 3-2
shows a typical input matching network for f
RF
= 315 MHz and f
RF
= 433.92 MHz
using a SAW.
Figure 3-3 on page 6
illustrates the input matching to 50Ω without a SAW. The
input matching networks shown in
Figure 3-3 on page 6
are the reference networks for the
parameters given in the electrical characteristics.
Table 3-1.
Conditions
Calculation of LO and IF Frequency
Local Oscillator Frequency
f
LO
= 314 MHz
f
LO
= 432.92 MHz
Intermediate Frequency
f
IF
= 1 MHz
f
IF
= 1 MHz
f
RF
= 315 MHz, MODE = 0
f
RF
= 433.92 MHz, MODE = 1
300 MHz < f
RF
< 365 MHz, MODE = 0
f
RF
f
LO
= -------------------
1
-
1
+ ---------
314
f
RF
f
LO
= ---------------------------
-
1
1
+ -----------------
-
432.92
f
LO
f
IF
= ---------
-
314
365 MHz < f
RF
< 450 MHz, MODE = 1
f
LO
-
f
IF
= -----------------
432.92
Figure 3-2.
Input Matching Network with SAW Filter
ATA5744
8
LNAGND
8
ATA5744
LNAGND
C3
22p
L
25n
9
LNA_IN
C3
47p
L
25n
9
LNA_IN
C16
C17
8.2p
TOKO LL2012
F27NJ
C16
C17
22p
TOKO LL2012
F47NJ
100p
f
RF
= 433.92 MHz
L3
27n
100p
f
RF
= 315 MHz
L2
TOKO LL2012
F82NJ
1
C2
10p
82n
2
IN
IN_GND
L3
47n
RF
IN
C2
8.2p
L2
TOKO LL2012
F33NJ
33n
1
2
IN
OUT
OUT_GND
IN_GND
CASE_GND
3, 4 7, 8
B3555
5
6
RF
IN
B3551
OUT
5
6
OUT_GND
CASE_GND
3, 4 7, 8
5
4893A–RKE–11/05
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
