Features
•
Minimal External Circuitry Requirements, No RF Components on the PC Board Except
•
•
•
•
•
•
•
•
•
•
Matching to the Receiver Antenna
High Sensitivity, Especially at Low Data Rates
Sensitivity Reduction Possible Even While Receiving
Fully Integrated VCO
Low Power Consumption Due to Configurable Self Polling with a Programmable Time
Frame Check
Supply Voltage 4.5V to 5.5V
Operating Temperature Range –40°C to +105°C
Single-ended RF Input for Easy Adaptation to
λ
/ 4 Antenna or Printed Antenna on PCB
Low-cost Solution Due to High Integration Level
ESD Protection According to MIL-STD. 883 (4 KV HBM) Except Pin POUT (2 KV HBM)
High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW
Front-end Filter
– Up to 40 dB is Thereby Achievable with Newer SAWs
Programmable Output Port for Sensitivity Selection or for Controlling External
Periphery
Communication to the Microcontroller Possible via a Single, Bi-directional Data Line
Power Management (Polling) is also Possible by Means of a Separate Pin via the
Microcontroller
2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)
UHF ASK
Receiver IC
ATA3741
•
•
•
•
1. Description
The ATA3741 is a multi-chip PLL receiver device supplied in an SO20 package. It has
been specially developed for the demands of RF low-cost data transmission systems
with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in
Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel's PLL
RF transmitter U2741B. Its main applications are in the areas of telemetering, security
technology, and keyless-entry systems. It can be used in the frequency receiving
range of f
0
= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-
ments made below refer to 433.92-MHz and 315-MHz applications.
4899B–RKE–10/06
Figure 1-1.
System Block Diagram
UHF ASK/FSK
Remote control transmitter
U2741B
UHF ASK/FSK
Remote control receiver
1 Li cell
ATR3741
Demod
Control
PLL
Antenna
Antenna
1...3
Encoder
ATARx9x
Keys
XTO
VCO
PLL
VCO
XTO
Power
amp.
LNA
Figure 1-2.
Block Diagram
V
S
FSK/ASK
CDEM
AVCC
ENABLE
SENS
IF Amp
Sensitivity
reduction
Polling circuit
and
control logic
TEST
POUT
MODE
4
th
Order
FE
CLK
DVCC
FSK/ASK
Demodulator
and data filter
RSSI
DEMOD_OUT
50 kΩ
DATA
Limiter out
AGND
DGND
MIXVCC
LPF
3 MHz
Standby logic
LFGND
LNAGND
IF Amp
LFVCC
LPF
3 MHz
VCO
XTO
XTO
f
LNA_IN
LNA
÷ 64
LF
2
ATA3741
4899B–RKE–10/06
Microcontroller
ATA3741
2. Pin Configuration
Figure 2-1.
Pinning SO20
SENS
FSK/ASK
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA
ENABLE
TEST
POUT
MODE
DVCC
XTO
LFGND
LF
LFVCC
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Description
Symbol
SENS
FSK/ASK
CDEM
AVCC
AGND
DGND
MIXVCC
LNAGND
LNA_IN
NC
LFVCC
LF
LFGND
XTO
DVCC
MODE
POUT
TEST
ENABLE
DATA
Function
Sensitivity-control resistor
Selecting FSK/ASK. Low: FSK, High: ASK
Lower cut-off frequency data filter
Analog power supply
Analog ground
Digital ground
Power supply mixer
High-frequency ground LNA and mixer
RF input
Not connected
Power supply VCO
Loop filter
Ground VCO
Crystal oscillator
Digital power supply
Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe)
Programmable output port
Test pin, during operation at GND
Enables the polling mode
Low: polling mode off (sleep mode)
High: polling mode on (active mode)
Data output/configuration input
3
4899B–RKE–10/06
3. RF Front End
The RF front end of the receiver is a heterodyne configuration that converts the input signal into
a 1-MHz IF signal. As seen in the block diagram, the front end consists of an LNA (low noise
amplifier), LO (local oscillator), a mixer, and an RF amplifier.
The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal
oscillator) generates the reference frequency f
XTO
. The VCO (voltage-controlled oscillator) gen-
erates the drive voltage frequency f
LO
for the mixer. f
LO
is dependent on the voltage at pin LF. f
LO
is divided by a factor of 64. The divided frequency is compared to f
XTO
by the phase frequency
detector. The current output of the phase frequency detector is connected to a passive loop filter
and thereby generates the control voltage V
LF
for the VCO. By means of that configuration, V
LF
is controlled in a way that f
LO
/ 64 is equal to f
XTO
. If f
LO
is determined, f
XTO
can be calculated
using the following formula:
f
LO
-
f
XTO
= -------
64
The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The
crystal should be connected to GND via a capacitor CL according to
Figure 3-1.
The value of the
capacitor is recommended by the crystal supplier. The value of CL should be optimized for the
individual board layout to achieve the exact value of f
XTO
and thereby of f
LO
. When designing the
system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be
considered.
Figure 3-1.
PLL Peripherals
V
S
DVCC
C
L
XTO
LFGND
LF
V
S
LFVCC
R1
C10
C9
R1 = 820Ω
C9 = 4.7 nF
C10 = 1 nF
The passive loop filter connected to pin LF is designed for a loop bandwidth of B
Loop
= 100 kHz.
This value for B
Loop
exhibits the best possible noise performance of the LO.
Figure 3-1
shows
the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo-
nents are changed for any reason, please note that the maximum capacitive load at pin LF is
limited. If the capacitive load is exceeded, a bit check may no longer be possible since f
LO
can-
not settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling
also will not work .
4
ATA3741
4899B–RKE–10/06
ATA3741
f
LO
is determined by the RF input frequency f
RF
and the IF frequency f
IF
using the following for-
mula:
f
LO
=
f
RF
–
f
IF
To determine f
LO
, the construction of the IF filter must be considered at this point. The nominal IF
frequency is f
IF
= 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter
is tuned by the crystal frequency f
XTO
. This means that there is a fixed relation between f
IF
and
f
LO
that depends on the logic level at pin mode. This is described by the following formulas:
f
LO
-
MODE
=
0 (USA) f
IF
= ---------
314
f
LO
MODE
=
1 (Europe) f
IF
= -----------------
-
432.92
The relation is designed to achieve the nominal IF frequency of f
IF
= 1 MHz for most applica-
tions. For applications where f
RF
= 315 MHz, MODE must be set to “0”. In the case of
f
RF
= 433.92 MHz, MODE must be set to ”1”. For other RF frequencies, f
IF
is not equal to 1 MHz.
f
IF
is then dependent on the logical level at pin MODE and on f
RF
.
Table 3-1
summarizes the dif-
ferent conditions.
The RF input either from an antenna or from a generator must be transformed to the RF input
pin LNA_IN. The input impedance of LNA_IN is specified in
“Electrical Characteristics” on page
23.
The parasitic board inductances and capacitances also influence the input matching. The RF
receiver ATA3741 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA.
Hence, noise matching is the best choice for designing the transformation network.
A good practice when designing the network is to start with power matching. From that starting
point, the values of the components can be varied to some extent to achieve the best sensitivity.
If a SAW is implemented into the input network, a mirror frequency suppression of
∆P
Ref
= 40 dB
can be achieved. There are SAWs available that exhibit a notch at
∆f
= 2 MHz. These SAWs
work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also
improved by using a SAW. In typical automotive applications, a SAW is used.
Figure 3-2 on page 6
shows a typical input matching network for f
RF
= 315 MHz and
f
RF
= 433.92 MHz using a SAW.
Figure 3-3 on page 6
illustrates an input matching to 50Ω with-
out a SAW. The input matching networks shown in
Figure 3-3
are the reference networks for the
parameters given in the
“Electrical Characteristics” on page 23.
Table 3-1.
Conditions
f
RF
= 315 MHz, MODE = 0
f
RF
= 433.92 MHz, MODE = 1
Calculation of LO and IF Frequency
Local Oscillator Frequency
f
LO
= 314 MHz
f
LO
= 432.92 MHz
f
RF
f
LO
= -------------------
1
-
1
+ ---------
314
f
RF
-
f
LO
= ---------------------------
1
-
1
+ -----------------
432.92
Intermediate Frequency
f
IF
= 1 MHz
f
IF
= 1 MHz
f
LO
f
IF
= ---------
-
314
300 MHz < f
RF
< 365 MHz, MODE = 0
365 MHz < f
RF
< 450 MHz, MODE = 1
f
LO
f
IF
= -----------------
-
432.92
5
4899B–RKE–10/06
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
