CAT25010/20/40
1K/2K/4K SPI Serial CMOS EEPROM
FEATURES
s
10 MHz SPI compatible
s
1.8 to 6.0 volt operation
s
Hardware and software protection
s
Zero standby current
s
Low power CMOS technology
s
SPI modes (0,0 & 1,1)*
s
Commercial, industrial, automotive and extended
s
100 year data retention
s
Self-timed write cycle
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
1,000,000 program/erase cycles
s
8-Pin DIP/SOIC, 8-Pin TSSOP and 8-Pin MSOP
s
16-byte page write buffer
s
Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
temperature ranges
DESCRIPTION
The CAT25010/20/40 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25010/20/40 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The
HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25010/
20/40 is designed with software and hardware write
protection features including Block Write protection. The
device is available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP
and 8-pin TSSOP packages.
PIN CONFIGURATION
SOIC Package (S, V)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
BLOCK DIAGRAM
MSOP Package (R, Z)*
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SENSE AMPS
SHIFT REGISTERS
SI
SI
*CAT 25010/20 only
DIP Package (P, L)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
TSSOP Package (U, Y)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCL
SI
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
E
2
PROM
ARRAY
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
NC
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
25C128 F02
* Other SPI modes available on request.
Doc. No. 1006, Rev. J
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT25010/20/40
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL(5)
V
IH(5)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
5
3
0
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
2.7V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
V
IN
= V
SS
or V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) V
IL
min and V
IH
max are reference values only and are not tested.
Doc. No. 1006, Rev. J
2
CAT25010/20/40
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, V
CC
=+5.0V.
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(3)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
500
500
500
150
150
0
250
150
100
100
100
50
50
100
100
5
250
0
75
50
100
100
100
50
50
Min.
50
50
250
250
DC
1
50
2
2
40
40
5
75
0
75
50
2.5V-6.0V
Max.
20
20
75
75
DC
5
50
2
2
40
40
5
40
4.5V-5.5V
Min.
20
20
40
40
DC
10
50
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
L
= 50pF
L
= 100pF
(note 2)
Test
UNITS Conditions
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
Max. Min.
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
=50pF
(3) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
3
Doc. No. 1006, Rev. J
CAT25010/20/40
FUNCTIONAL DESCRIPTION
The CAT25010/20/40 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25010/20/40 to interface
directly with many of today’s popular microcontrollers.
The CAT25010/20/40 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
Figure 1. Sychronous Data Timing
V
IH
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25010/20/40. During a read
cycle, data is shifted out on the falling edge of the serial
t
CS
CS
V
IL
t
CSS
V
IH
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
t
HO
t
DIS
HI-Z
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Note:
(1) X=0 for 25010, 25020. X=A8 for 25040
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1006, Rev. J
4
CAT25010/20/40
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When
WP
is tied low all write operations are inhibited.
WP
held low while
CS
is low will interrupt a write to the
CAT25010/20/40. If the internal write cycle has already
been initiated,
WP
going low will have no effect on any
write operation. Figure 10 illustrates the
WP
timing
sequence during a write operation.
HOLD
Hold
HOLD:
The
HOLD
pin is used to pause transmission to the
CAT25010/20/40 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (HOLD should be held
high any time this function is not being used.)
HOLD
may
be tied high directly to V
CC
or tied to V
CC
through a
resistor. Figure 9 illustrates hold timing sequence.
clock for SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25010/20/40. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25010/
20/40 and
CS
high disables the CAT25010/20/40.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25010/
20/40 draws ZERO current in the Standby mode. A high
to low transition on
CS
is required prior to any sequence
being initiated. A low to high transition on
CS
after a valid
write sequence is what initiates an internal write cycle.
STATUS REGISTER
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
0
1
Array Address
Protected
None
25010: 60-7F
25020: C0-FF
25040: 180-1FF
25010: 40-7F
25020: 80-FF
25040: 100-1FF
25010: 00-7F
25020: 00-FF
25040: 000-1FF
Protection
No Protection
Quarter Array Protection
1
0
Half Array Protection
1
1
Full Array Protection
5
Doc. No. 1006, Rev. J
FPGA/CPLD
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