ACTS08MS
April 1995
Radiation Hardened
Quad 2-Input AND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10
-10
Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm
2
/mg
• Dose Rate Upset >10
11
RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current
≤1µA
at VOL, VOH
14 LEAD CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
Description
The Intersil ACTS08MS is a radiation hardened quad 2-Input
AND Gate. A high on both inputs forces the output to a high
logic level.
The ACTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of a
radiation hardened, high-speed, CMOS/SOS Logic Family.
A2
B2
Y2
GND
Ordering Information
PART NUMBER
ACTS08DMSR
ACTS08KMSR
ACTS08D/Sample
ACTS08K/Sample
ACTS08HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
Truth Table
INPUTS
An
L
L
H
H
Bn
L
H
L
H
OUTPUT
Yn
L
L
L
H
Functional Diagram
(1, 4, 9, 12)
An
(3, 6, 8, 11)
Yn
NOTE: L = Logic Level Low, H = Logic Level High
(2, 5, 10, 13)
Bn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
1
518851
File Number
3994
Specifications ACTS08MS
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.0V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
DC Drain Current, Any One Output.
. . . . . . . . . . . . . . . . . . . . . .±50mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265
o
C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
(All voltages reference to VSS)
Reliability Information
Thermal Impedance
θ
JA
θ
JC
o
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74 C/W
24
o
C/W
o
C/W
30
o
C/W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Maximum Package Power Dissipation at +125
o
C
DIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7W
Flatpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4W
Maximum Device Power Dissipation. . . . . . . . . . . . . . . . . . .(TBD)W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Gates
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent
damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed
under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.
Operating Conditions
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . 10ns/ V Max
Operating Temperature Range (T
A
) . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . VCC to VCC/2V
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
1
2, 3
1, 2, 3
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
MIN
-
-
-
MAX
5
100
1.6
UNITS
µA
µA
mA
PARAMETER
Supply Current
SYMBOL
ICC
(NOTE 1)
CONDITIONS
VCC = 5.5V,
VIN = VCC or GND
VCC = 5.5V
VIN = VCC or GND
1 Input = 3.4V
VCC = VIH = 4.5V,
VOUT = VCC -0.4V,
VIL = 0V (Note 2)
VCC = VIH = 4.5V,
VOUT = 0.4V,
VIL = 0V (Note 2)
VCC = 5.5V, VIH = 2.75V,
IOH = -50µA, VIL = 0.80V
VCC = 4.5V, VIH = 2.25V,
IOH = -50µA, VIL = 0.8V
Delta ICC
DICC
Output Current
(Source)
Output Current
(Sink)
Output Voltage High
IOH
1
2, 3
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2, 3
7, 8A, 8B
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
-12
-8
12
8
VCC -0.1
VCC -0.1
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
±0.5
±1.0
-
mA
mA
mA
mA
V
V
V
V
µA
µA
V
IOL
VOH
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V,
IOL = 50µA, VIL = 0.80V
VCC = 4.5V, VIH = 2.25V,
IOL = 50µA, VIL = 0.80V
Input Leakage
Current
Noise Immunity
Functional Test
NOTE:
IIN
VCC = 5.5V,
VIN = VCC or GND
VCC = 4.5V, VIH = 2.25V,
VIL = 0.8V (Note 3)
FN
1. All voltages reference to device GND.
2. Force/measure functions may be interchanged.
3. Per functional tests, VO
≥4.0V
is recognized as a logic “1”, and VO
≤0.5V
is recognized as a logic “0”.
Spec Number
2
518851
Specifications ACTS08MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP
A SUB-
GROUPS
9
10, 11
9
10, 11
LIMITS
TEMPERATURE
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
MIN
2
2
2
2
MAX
13
15
14
15
UNITS
ns
ns
ns
ns
PARAMETER
Propagation Delay
Input to Output
SYMBOL
TPHL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
VCC = 4.5V, VIH = 3.0V,
VIL = 0V
TPLH
NOTES:
1. All voltages referenced to device GND.
2. Measurements made with RL = 500Ω, CL = 50pF, Input TR = TF = 3ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Capacitance Power
Dissipation
Input Capacitance
SYMBOL
CPD
CONDITIONS
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
VCC = 5.0V, VIH = 5.0V,
VIL = 0V, f = 1MHz
NOTE
1
1
1
1
TEMP
+25
o
C
+125
o
C
+25
o
C
+125
o
C
MIN
-
-
-
-
TYP
TBD
TBD
-
-
MAX
-
-
10
10
UNITS
pF
pF
pF
pF
CIN
NOTE:
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly
tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
(NOTES 1, 2)
CONDITIONS
VCC = 5.5V, VIN = VCC or GND
VCC - 5.5V, VIN = VCC or GND
1 Input = 3.4V
VCC = VIH = 4.5V, VIL = 0,
VOUT = VCC -0.4V
VCC = VIH = 4.5V, VIL = 0,
VOUT = 0.4V
VCC = 5.5V, VIH = 2.75V,
VIL = 0.80V, IOH = -50µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V, IOH = -50µA
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V,
VIL = 0.80V, IOH = 50µA
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V, IOH = 50µA
Input Leakage Current
Noise Immunity
Functional Test
Propagation Delay
Input to Output
NOTES:
1. All voltages referenced to device GND.
2. For functional tests, VO
≥4.0V
is recognized as a logic “1”, and VO
≤0.5V
is recognized as a logic “0”.
IIN
FN
TPHL,
TPLH
VCC = 5.5V, VIN = VCC or GND
VCC = 4.5V, VIH = 2.25V,
VIL = 0.80V (Note 2)
VCC = 4.5V, VIH = 3.0V, VIL = 0V
RAD LIMITS
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-8
8
VCC -0.1
VCC -0.1
-
-
-
-
2
MAX
100
1.6
-
-
-
-
0.1
0.1
±1
-
15
UNITS
µA
mA
mA
mA
V
V
V
V
µA
V
ns
PARAMETER
Supply Current
Delta ICC
Output Current (Source)
Output Current (Sink)
Output Voltage High
SYMBOL
ICC
ICC
IOH
IOL
VOH
Spec Number
3
518851
Specifications ACTS08MS
TABLE 5. DELTA PARAMETERS (+25
o
C)
PARAMETER
Supply Current
Output Current
NOTE:
1. All delta calculations are referenced to 0 hour readings or pre-life readings.
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
Initial Test (Preburn-In)
Interim Test 1 (Postburn-In)
Interim Test 2 (Postburn-In)
PDA
Interim Test 3 (Postburn-In)
PDA
Final Test
Group A (Note 1)
Group B
Group D
NOTE:
1. Alternate Group A testing may be exercised in accordance with MIL-STD-883, Method 5005.
Subgroup B-5
Subgroup B-6
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
100%/5004
Sample/5005
Sample/5005
Sample/5005
Sample/5005
GROUP A SUBGROUPS
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
1, 7, 9
Subgroups 1, 2, 3, 9, 10, 11
ICC, IOL/H
READ AND RECORD
ICC, IOL/H
ICC, IOL/H
ICC, IOL/H
ICC
IOL/IOH
SYMBOL
(NOTE 1)
DELTA LIMIT
±1.0
±15
UNITS
µA
%
TABLE 7. TOTAL DOSE IRRADIATION
TEST
CONFORMANCE GROUP
Group E Subgroup 2
NOTE:
1. Except FN test which will be performed 100% Go/No-Go.
TABLE 8. BURN-IN TEST CONNECTIONS (+125
o
C < TA < 139
o
C)
OSCILLATOR
OPEN
-
GROUND
1, 2, 4, 5, 7, 9, 10,
12, 13
7
7
1/2 VCC = 3V
±0.5V
3, 6, 8, 11
VCC = 6V
±0.5V
14
50kHz
-
25kHz
-
STATIC BURN-IN I (Note 1)
METHOD
5005
PRE RAD
1, 7, 9
POST RAD
Table 4
1, 9
READ AND RECORD
PRE RAD
POST RAD
Table 4 (Note 1)
STATIC BURN-IN II (Note 1)
-
-
NOTE:
1. Each pin except VCC and GND will have a series resistor of 500Ω
±5%.
TABLE 9. IRRADIATION TEST CONNECTIONS (TA = +25
o
C,
±5
o
C)
FUNCTION
Irradiation Circuit (Note 1)
NOTE:
1. Each pin except VCC and GND will have a series resistor of 47kΩ
±5%.
Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures.
OPEN
3, 6, 8, 11
GROUND
7
VCC = 5V
±0.5V
1, 2, 4, 5, 9, 10, 11, 12, 13, 14
3, 6, 8, 11
3, 6, 8, 11
1, 2, 4, 5, 9, 10, 12, 13, 14
14
-
1, 2, 4, 5, 9, 10, 12, 13
-
-
DYNAMIC BURN-IN TEST CONNECTIONS (Note 1)
Spec Number
4
518851
Specifications ACTS08MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65
o
to +150
o
C)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125
100% Interim Electrical Test 1 (Note 1)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
o
C
100% Static Burn-In 2 Method 1015, 24 Hours at +125
o
C Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125
o
C
or 180 Hours at +135
o
C
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
Min
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
Propagation Delay Timing Diagram and Load Circuit
DUT
VIH
VS
VSS
TPLH
TPHL
VOH
VS
VOL
OUTPUT
INPUT
CL
50pF
TEST
POINT
RL
500Ω
AC VOLTAGE LEVELS
PARAMETER
VCC
VIH
VS
VIL
GND
ACTS
4.50
3.00
1.30
0
0
UNITS
V
V
V
V
V
Spec Number
5
518851
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