37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
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Operationally equivalent to Xilinx
XC1700 family
Wide voltage range 3.0 V to 6.0 V
Maximum read current 10 mA at 5.0 V
Standby current 100
µA
typical
Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
Full Static Operation
Sequential Read/Program
Cascadable Output Enable
10 MHz Maximum Clock Rate @ 5.0 Vdc
Programmable Polarity on Hardware Reset
Programming with industry standard EPROM pro-
grammers
Electrostatic discharge protection > 4,000 volts
8-pin PDIP/SOIC and 20-pin PLCC packages
Data Retention > 200 years
Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial:
-40°C to +85°C
PACKAGE TYPES
PDIP
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
SOIC
DATA
CLK
RESET/OE
CE
1
8
V
CC
V
PP
CEO
V
SS
37LV36
37LV65
37LV128
2
3
4
7
6
5
PLCC
DATA V
CC
20
12
19
18
17
V
PP
16
15
14
CEO
13
3
2
10
1
11
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V V
CC
range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device
37LV36
37LV65
37LV128
Bits
36,288
65,536
131,072
Programming Word
1134 x 32
2048 x 32
4096 x 32
CLK
4
5
37LV36
37LV65
37LV128
9
RESET/OE
6
7
CE
8
Vss
BLOCK DIAGRAM
Xilinx is a registered trademark of Xilinx Corporation.
1998 Microchip Technology Inc.
DS21109E-page 1
37LV36/65/128
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
DATA
CLK
PIN FUNCTION TABLE
Function
Data I/O
Clock Input
8
1
2
3
4
5
6
7
8
20
2
4
6
8
10
14
17
20
V
CC
and input voltages w.r.t. V
SS
.......... -0.6V to +0.6V
V
PP
voltage w.r.t. V
SS
during
programming ...................................... -0.6V to +14.0V
Output voltage w.r.t. V
SS
................-0.6V to V
CC
+0.6V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied......-65°C to +125°C
Soldering temperature of leads (10 sec.) ......... +300°C
ESD protection on all pins
..................................... ≥
4 kV
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
RESET/OE Reset Input and Output
Enable
CE
V
SS
CEO
V
PP
V
CC
Chip Enable Input
Ground
Chip Enable Output
Programming Voltage Supply
+3.0V to 6.0V Power Supply
Not Labeled Not utilized, not connected
TABLE 1-2:
READ OPERATION DC CHARACTERISTICS
V
CC
= +3.0 to 6.0V
Commercial (C):
Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
DATA, CE, CEO and Reset pins:
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input Leakage
Output Leakage
Input Capacitance
(all inputs/outputs)
Operating Current
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
LI
I
LO
C
INT
I
CC
Read
Min.
2.0
-0.3
3.86
2.4
—
-10
-10
—
—
—
—
Max.
V
CC
0.8
Units
V
V
V
V
µA
µA
pF
mA
mA
µA
µA
Conditions
.32
10
10
10
10
2
100
50
I
OH
= -4 mA V
CC
≥
4.5V
I
OH
= -4 mA V
CC
≥
3.0V
I
OL
= 4.0 mA
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
Tamb = 25°C; F
CLK
= 1 MHz (Note 1)
V
CC
= 6.0V, CLK = 10 MHz
V
CC
= 3.6V, CLK = 2.5 MHz
Outputs open
V
CC
= 6.0V, CE = 5.8V
V
CC
= 3.6V, CE = 3.4V
Standby Current
I
CCS
Note 1: This parameter is initially characterized and not 100% tested.
DS21109E-page 2
1998 Microchip Technology Inc.
37LV36/65/128
2.0
2.1
DATA
Data I/O
8.0
CASCADING SERIAL EPROMS
Three-state DATA output for reading and input during
programming.
Cascading Serial EPROMs provide additional memory
for multiple FPGAs configured as a daisy-chain, or for
future applications requiring larger configuration mem-
ories.
When the last bit from the first Serial EPROM is read,
the next clock signal to the Serial EPROM asserts its
CEO output LOW and disables its DATA line. The sec-
ond Serial EPROM recognizes the LOW level on its CE
input and enables its DATA output.
When configuration is complete, the address counters
of all cascaded Serial EPROMs are reset if RESET
goes LOW forcing the RESET/OE on each Serial
EPROM to go HIGH. If the address counters are not to
be reset upon completion, then the RESET/OE inputs
can be tied to ground.
Additional logic may be required if cascaded memories
are so large that the rippled chip enable is not fast
enough to activate successive Serial EPROMs.
3.0
3.1
CLK
Clock Input
Used to increment the internal address and bit
counters for reading and programming.
4.0
4.1
RESET/OE
Reset Input and Output Enable
A LOW level on both the CE and RESET/OE inputs
enables the data output driver. A HIGH level on
RESET/OE resets both the address and bit counters.
In the 37LVXXX, the logic polarity of this input is pro-
grammable as either RESET/OE or OE/RESET. This
document describes the pin as RESET/OE although
the opposite polarity is also possible. This option is
defined and set at device program time.
9.0
STANDBY MODE
5.0
5.1
CE
Chip Enable Input
The 37LVXXX enters a low-power Standby Mode
whenever CE is HIGH. In Standby Mode, the Serial
EPROM consumes less than 100
µA
of current. The
output will remain in a high-impedance state regardless
of the state of the OE input.
CE is used for device selection. A LOW level on both
CE and OE enables the data output driver. A HIGH
level on CE disables both the address and bit counters
and forces the device into a low power mode.
10.0
PROGRAMMING MODE
6.0
6.1
CEO
Chip Enable Output
Programming Mode is entered by holding V
PP
HIGH
(+13 volts) for two clock edges and then holding V
PP
=
V
DD
for one clock edge. Programming mode is exited
by driving a LOW on both CE and OE and then remov-
ing power from the device. Figures 4 through 7 show
the programming algorithm.
This signal is asserted LOW on the clock cycle follow-
ing the last bit read from the memory. It will stay LOW
as long as CE and OE are both LOW. It will then follow
CE until OE goes HIGH. Thereafter, CEO will stay
HIGH until the entire EPROM is read again. This pin
also used to sense the status of RESET polarity when
Programming Mode is entered.
11.0
37LVXXX RESET POLARITY
The 37LVXXX lets the user choose the reset polarity as
either RESET/OE or OE/RESET. Any third-party com-
mercial programmer should prompt the user for the
desired reset polarity.
The programming of the overflow word should be han-
dled transparently by the EPROM programmer; it is
mentioned here as supplemental information only.
The polarity is programmed into the first overflow word
location, maximum address+1. 00000000 in these
locations makes the reset active LOW, FFFFFFFF in
these locations makes the reset active HIGH. The
default condition is RESET active HIGH.
7.0
7.1
VPP
Programming Voltage Supply
Used to enter programming mode (+13 volts) and to
program the memory (+13 volts). Must be connected
directly to Vcc for normal Read operation. No over-
shoot above +14 volts is permitted.
1998 Microchip Technology Inc.
DS21109E-page 3
37LV36/65/128
FIGURE 11-1: READ CHARACTERISTICS TIMING
TABLE 11-1:
READ CHARACTERISTICS
AC Testing Waveform: V
IL
= 0.2V; V
IH
= 3.0V
AC Test Load: 50 pF
V
OL
= V
OL
_MAX; V
OH
= V
OH
_MIN
Limits 3.0V
≤
Vcc
≤
6.0V
Min.
Max.
45
60
200
—
50
—
—
—
—
—
—
Limits 4.5V
≤
Vcc
≤
6.0V
Min.
—
—
—
0
—
25
25
25
80
0
0
20
2.5
—
Max.
45
50
60
—
50
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Note 1
Note 1
Notes 1, 2
Symbol
Parameter
Units
Conditions
T
OE
T
CE
T
CAC
T
OH
T
DF
T
LC
T
HC
T
SCE
T
SCED
T
HCE
T
HCED
T
HOE
CLK max
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Set up Time to CLK
(to guarantee proper counting)
CE setup time to CLK
(to guarantee proper DATA read)
CE Hold Time to CLK
(to guarantee proper counting)
CE hold time to CLK
(to guarantee proper DATA read)
OE High Time
(Guarantees counters are Reset)
Clock Frequency
—
—
—
0
—
100
100
40
100
0
50
100
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kΩ to V
LOAD
= V
CC
/2.
DS21109E-page 4
1998 Microchip Technology Inc.
37LV36/65/128
FIGURE 11-2: READ CHARACTERISTICS AT END OF ARRAY TIMING
TABLE 11-2:
READ CHARACTERISTICS AT END OF ARRAY
AC Testing Waveform: V
IL
= 0.2V; V
IH
= 3.0V
AC Test Load: 50 pF
V
OL
= V
OL
_MAX; V
OH
= V
OH
_MIN
Limits 3.0V
≤
Vcc
≤
Limits 4.5V
≤
Vcc
≤
6.0V
6.0V
Min.
Max.
50
65
45
45
Min.
—
—
—
—
Max.
50
40
40
40
ns
ns
ns
ns
Notes 1, 2
Symbol
Parameter
Units
Conditions
T
CDF
T
OCK
T
OCE
T
OOE
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
—
—
—
—
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kΩ to V
LOAD
= V
CC
/2.
1998 Microchip Technology Inc.
DS21109E-page 5
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