Product Specification
PE3501
Product Description
The PE3501 is a high-performance dynamic UltraCMOS™
prescaler with a fixed divide ratio of 2. Its operating frequency
range is 400 MHz to 3.5 GHz. The PE3501 operates on a
nominal 3 V supply and draws only 12 mA. It is packaged in a
small 8-lead TSSOP and is ideal for frequency scaling and
microwave PLL synthesis solutions.
The PE3501 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
3500 MHz Low Power UltraCMOS™
Divide-by-2 Prescaler
Features
•
High-frequency operation:
400 MHz to 3500 MHz
•
Fixed divide ratio of 2
•
Low-power operation: 12 mA typical
@3V
•
Small package: 8-lead TSSOP
•
Low cost
Figure 2. Package Type
8-lead TSSOP
D
Q
DRIVER
OUTPUT BUFFER
F
out
F
in
PREAMP
CLK
DEC
QB
OFF-CHIP
BYPASS
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω
)
V
DD
= 3.0 V, -40° C
≤
T
A
≤
85° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Input Frequency (F
in
)
Input Power (P
in
)
Conditions
Minimum
2.85
Typical
3.0
12
Maximum
3.15
15
3500
+10
+10
Units
V
mA
MHz
dBm
dBm
dBm
dBm
400
400 MHz
≤
F
in
≤
3000 MHz
3000 MHz < F
in
≤
3500 MHz
400 MHz
≤
F
in
≤
3000 MHz
3000 MHz < F
in
≤
3500 MHz
-10
0
-10
-15
Output Power (P
out
)
Document No. 70-0111-03
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 8
PE3501
Product Specification
Figure 3. Pin Configuration (Top View)
1
8
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
V
DD
GND
F
IN
2
7
F
OUT
3501
DEC
3
4
6
5
NC
GND
GND
Table 2. Pin Descriptions
Pin
No.
1
2
3
Pin
Name
V
DD
F
in
DEC
Description
Power supply pin. Bypassing is required.
Input signal pin. DC blocking capacitor
required (15 pF typical)
Power supply decoupling pin. Place a ca-
pacitor as close as possible and connect
directly to the ground plane.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Ground pin.
No Connection. This pin should be left
open.
Divided frequency output pin. DC blocking
capacitor required (47 pF typical)
Ground pin.
Device Functional Considerations
The PE3501 divides a 400 MHz to 3500 MHz
input signal by two, producing a 200 MHz to 1750
MHz output signal. To work properly, pin 3 must
be supplied with a bypass capacitor to ground. In
addition, the input and output signals (pins 2 & 7)
must be AC coupled via an external capacitor, as
shown in the test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 11 for a layout example.
4
5
6
7
8
GND
GND
NC
F
out
GND
Table 3. Absolute Maximum Ratings
Symbol
V
DD
P
in
T
ST
T
OP
V
ESD
Parameter/Conditions
Supply voltage
Input Power
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model)
Min
Max
4.0
15
Units
V
dBm
°C
°C
V
-65
-40
150
85
250
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage. Exposure
to absolute maximum ratings for extended periods
may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Document No. 70-0111-03
│
UltraCMOS™ RFIC Solutions
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
