UXN14M32K
15 GHz Divide-by-1 to 232-1
32-Bit Programmable Integer Divider
Features
• Wide operating range: DC-15 GHz
• Divide ratios: 1 to 2
32
-1
• Large output swings: 0.8 Vpp/side
• Adjustable output amplitude
• Single-ended or differential drive
• Serial Control Lines
• Low SSB phase noise
• Ceramic 4 mm x 4 mm package
• USB powered eval board with PC
interface
Application
The SuperDivider can be used as a gen-
eral purpose, highly configurable, divider
in a variety of high frequency synthesiz-
er applications.
Pad Metallization
The QFN package pad metallization is
500-1000 micro-inches of Sn63 solder
dip.
Description
The SuperDivider is a highly programmable
integer divider covering all integer divide ratios
between 1 and 4,294,967,295 (232-1). The
device features single-ended or differential
inputs and outputs. 3-wire serial control inputs
are CMOS and LVTTL compatible for ease
of system integration. The SuperDivider is
packaged in a 24-pin, 4 mm x 4 mm leadless
ceramic surface mount package.
A Windows PC user interface is available with
the eval board (UXN14M32KE). The interface
makes it convenient to adjust the output
amplitude and the divide ratio. It is powered
by USB bus so it is easy to use. Just plug the
UXN14M32KE into your PC, install the Mi-
crosemi software, and you are using the most
powerful frequency divider on the market.
Key Characteristics @ 25˚C:
VEE= -3.3 V, IEE=110-220 mA, Zi=50 Ω, Zo=60Ω
Parameter
Fin (GHz)
Pin (dBm)
Vout (Vpp)
PDC (W)
θjc (ºC/W)
1
2
Description
Input Frequency
Input Power
Output Voltage Per Side
DC Power Dissipation
2
Junction-Case Thermal Resistance
Min
DC
1
-20
-
0.3
-
Typ
-
0
0.8
-
51
Max
15
10
-
0.8
-
Low frequency dependent on input edge speed
Depends on divide ratio
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Subject to Change Without Notice
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UXN14M32K
Functional Block Diagram
Table 1: Pin Description
Port Name
INP
INN
OUTP
OUTN
VCC
VEE
LE
DAT
CLK
HLD
RST
VADJ
TEMP
Description
Divider input, positive terminal
Divider input, negative terminal
Divider output, positive terminal
Divider output, negative terminal
RF & DC ground
-3.3 V @ 220 mA
Load enable
Serial data input
Serial clock input
Output hold control
Divider reset control
Output amplitude control
Temperature diode
Notes
CML signal levels
CML signal levels
Requires DC return path to VCC
Requires DC return path to VCC
-
Negative supply voltage
CMOS levels, defaults to logic 0
CMOS levels, defaults to logic 0
CMOS levels, defaults to logic 0
CMOS levels, defaults to logic 0
CMOS levels, defaults to logic 0
Tie to VCC via resistor, refer to text for value
Optional temperature diode, refer to text
Simplified Control Logic Schematic
Table 2: Pin Description
Logic Level
1 (High)
0 (Low)
Minimum
VCC-1.25 V
VEE
Typical
VCC
VEE
Maximum
VCC
VEE+1.25 V
SMD-00103 Rev E
Subject to Change Without Notice
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UXN14M32K
Programming Divide Ration
Note: Maximum CLK frequency is estimated to be 30 MHz.
Equation 1
Divider Modulus = N = P0 · 20 + P1 · 21 + P2 · 22 + ... + P31 · 231
for 1 < N < (232-1)
Note: When N=0, HLD must be pulled high to ensure that the output does not enter meta-stable state.
Table 3: OEE vs. Divide Ratio
N
0
1
2-3
4-7
8-15
16-31
32-63
≥64
IEE (mA)
110
135
165
180
190
200
210
220
SMD-00103 Rev E
Subject to Change Without Notice
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