R32C/117 Group Datasheet
Datasheet
R32C/117 Group
RENESAS MCU
R01DS0064EJ0120
Rev.1.20
Feb 6, 2013
1.
1.1
Overview
Features
The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM
code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing
in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from
low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral
functions, provides support for a vast range of application fields.
The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory
space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,
multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-
chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I
2
C, and watchdog timer
enables to minimize external components.
The R32C/117 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin
and 144-pin plastic molded LQFP packages, has nine channels of serial interface, one channel of multi-
master I
2
C-bus interface, and one channel of CAN module.
1.1.1
Applications
Car audio, audio, printer, office/industrial equipment, etc.
R01DS0064EJ0120 Rev.1.20
Feb 6, 2013
Page 1 of 109
R32C/117 Group
1. Overview
1.1.2
Performance Overview
Tables 1.1 to 1.4 list the performance overview of the R32C/117 Group.
Table 1.1
Unit
CPU
Performance Overview for the 144-pin Package (1/2)
Function
Central
processing unit
Explanation
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit
64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit
64-bit
• IEEE-754 compatible FPU: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional
(1)
)
Flash memory: 384 Kbytes to 1 Mbyte
RAM: 40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for each product’s memory size
Low voltage
detector
Clock generator
Optional
(1)
Low voltage detection interrupt
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16/32 bits)
Interrupt vectors: 261
External interrupt inputs:
NMI, INT
× 9, key input × 4
Interrupt priority levels: 7
15 bits × 1 (selectable input frequency from prescaler output)
4 channels
• Cycle-steal transfer mode
• Request sources: 57
• 2 transfer modes: Single transfer, repeat transfer
• Triggered by an interrupt request of any peripheral
• 3 characteristic transfer functions: Immediate data transfer,
calculation result transfer, chain transfer
• 2 input-only ports
• 120 CMOS I/O ports (of which 32 are 5 V tolerant)
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
DMAC
Memory
Voltage
Detector
Clock
External Bus
Expansion
Bus and memory
expansion
Interrupts
Watchdog Timer
DMA
DMAC II
I/O Ports
Programmable
I/O ports
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
R01DS0064EJ0120 Rev.1.20
Feb 6, 2013
Page 2 of 109
R32C/117 Group
1. Overview
Table 1.2
Unit
Timer
Performance Overview for the 144-pin Package (2/2)
Function
Timer A
Explanation
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Timer B
Three-phase
motor control
timer
Serial
Interface
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
• I
2
C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional
(1)
) (UART0 to UART6)
10-bit resolution × 34 channels
Sample and hold functionality integrated
8-bit resolution × 2
CRC-CCITT (X
16
+ X
12
+ X
5
+ 1)
16 bits × 16 bits
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 24
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional
(1)
)
1 channel
1 channel
CAN functionality compliant with ISO 11898-1
32 mailboxes
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
144-pin plastic molded LQFP (PLQP0144KA-A)
A/D Converter
D/A Converter
CRC Calculator
X-Y Converter
Intelligent I/O
Multi-master I
2
C-bus Interface
CAN Module
Flash Memory
Operating Frequency/Supply
Voltage
Operating Temperature
Current Consumption
Package
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
R01DS0064EJ0120 Rev.1.20
Feb 6, 2013
Page 3 of 109
R32C/117 Group
1. Overview
Table 1.3
Unit
CPU
Performance Overview for the 100-pin Package (1/2)
Function
Central
processing unit
Explanation
R32C/100 Series CPU Core
• Basic instructions: 108
• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)
• Multiplier: 32-bit × 32-bit
64-bit
• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit
64-bit
• IEEE-754 compatible FPU: Single precision
• 32-bit barrel shifter
• Operating mode: Single-chip mode, memory expansion mode,
microprocessor mode (optional
(1)
)
Flash memory: 128 Kbytes to 1 Mbyte
RAM: 20 K/40 K/48 K/63 Kbytes
Data flash: 4 Kbytes × 2 blocks
Refer to Table 1.5 for each product’s memory size
Low voltage
detector
Clock generator
Optional
(1)
Low voltage detection interrupt
• 4 circuits (main clock, sub clock, PLL, on-chip oscillator)
• Oscillation stop detector: Main clock oscillator stop/restart detection
• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable
• Low power modes: Wait mode, stop mode
• Address space: 4 Gbytes (of which up to 64 Mbytes is user
accessible)
• External bus Interface: Support for wait-state insertion, 4 chip select
outputs
• Bus format: Separate bus/Multiplexed bus selectable, data bus width
selectable (8/16 bits)
Interrupt vectors: 261
External interrupt inputs:
NMI, INT
× 6, key input × 4
Interrupt priority levels: 7
15 bits × 1 (selectable input frequency from prescaler output)
4 channels
• Cycle-steal transfer mode
• Request sources: 51
• 2 transfer modes: Single transfer, repeat transfer
• Triggered by an interrupt request of any peripheral
• 3 characteristic transfer functions: Immediate data transfer,
calculation result transfer, chain transfer
• 2 input-only ports
• 84 CMOS I/O ports (of which 32 are 5 V tolerant)
• A pull-up resistor is selectable for every 4 input ports (except 5 V
tolerant inputs)
DMAC
Memory
Voltage
Detector
Clock
External Bus
Expansion
Bus and memory
expansion
Interrupts
Watchdog Timer
DMA
DMAC II
I/O Ports
Programmable
I/O ports
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
R01DS0064EJ0120 Rev.1.20
Feb 6, 2013
Page 4 of 109
R32C/117 Group
1. Overview
Table 1.4
Unit
Timer
Performance Overview for the 100-pin Package (2/2)
Function
Timer A
Explanation
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse-width
modulation (PWM) mode
Two-phase pulse signal processing in event counter mode (two-
phase encoder input) × 3
16-bit timer × 6
Timer mode, event counter mode, pulse frequency measurement
mode, pulse-width measurement mode
Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)
8-bit programmable dead time timer
Timer B
Three-phase
motor control
timer
Serial
Interface
UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels
• I
2
C-bus (UART0 to UART6)
• Special mode 2 (UART0 to UART6)
• IEBus (optional
(1)
) (UART0 to UART6)
10-bit resolution × 26 channels
Sample and hold functionality integrated
8-bit resolution × 2
CRC-CCITT (X
16
+ X
12
+ X
5
+ 1)
16 bits × 16 bits
Time measurement (input capture): 16 bits × 16
Waveform generation (output compare): 16 bits × 19
Serial interface: Variable-length synchronous serial I/O mode, IEBus
mode (optional
(1)
)
1 channel
1 channel
CAN functionality compliant with ISO 11898-1
32 mailboxes
Programming and erasure supply voltage: VCC = 3.0 to 5.5 V
Minimum endurance: 1,000 program/erase cycles
Security protection: ROM code protect, ID code protect
Debugging: On-chip debug, on-board flash programming
64 MHz (high speed version)/VCC = 3.0 to 5.5 V
50 MHz (normal speed version)/VCC = 3.0 to 5.5 V
-20°C to 85°C (N version)
-40°C to 85°C (D version)
-40°C to 85°C (P version)
45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)
35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)
8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)
100-pin plastic molded LQFP (PLQP0100KB-A)
A/D Converter
D/A Converter
CRC Calculator
X-Y Converter
Intelligent I/O
Multi-master I
2
C-bus Interface
CAN Module
Flash Memory
Operating Frequency/Supply
Voltage
Operating Temperature
Current Consumption
Package
Note:
1. Contact a Renesas Electronics sales office to use the optional features.
R01DS0064EJ0120 Rev.1.20
Feb 6, 2013
Page 5 of 109
FPGA/CPLD
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