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N25Q032A13EF4A0F: 产品描述FLASH - NOR 存储器 IC 32Mb SPI 108 MHz 8-UFDFPN（MLP8）（4x3）; 产品类别半导体存储器; 文件大小807KB，共83页; 制造商Alliance Memory; 标准

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N25Q032A13EF4A0F概述

FLASH - NOR 存储器 IC 32Mb SPI 108 MHz 8-UFDFPN（MLP8）（4x3）

N25Q032A13EF4A0F规格参数

参数名称	属性值
类别
厂商名称	Alliance Memory
包装	卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带
存储器类型	非易失
存储器格式	闪存
技术	FLASH - NOR
存储容量	32Mb
存储器组织	8M x 4
存储器接口	SPI
时钟频率	108 MHz
写周期时间 - 字，页	5ms
电压 - 供电	2.7V ~ 3.6V
工作温度	-40°C ~ 125°C（TA）
安装类型	表面贴装型
封装/外壳	8-UDFN 裸露焊盘
供应商器件封装	8-UFDFPN（MLP8）（4x3）
基本产品编号	N25Q032A13

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32Mb, 3V, Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB Sector Erase

N25Q032A

Features

•

SPI-compatible serial bus interface

108 MHz (MAX) clock frequency

2.7–3.6V single supply voltage

Dual/quad I/O instruction provides increased

throughput up to 432 MHz

Supported protocols

– Extended SPI, dual I/O, and quad I/O

Execute-in-place (XIP) mode for all three protocols

– Configurable via volatile or nonvolatile registers

– Enables memory to work in XIP mode directly af-

ter power-on

PROGRAM/ERASE SUSPEND operations

Continuous read of entire memory via a single com-

mand

– FAST READ

– QUAD or DUAL OUTPUT FAST READ

– QUAD or DUAL I/O FAST READ

Flexible to fit application

– Configurable number of dummy cycles

– Configurable output buffer

– RESET function available upon customer request

64-byte, user-lockable, one-time programmable

(OTP) dedicated area

Erase capability

– Subsector erase 4KB uniform granularity blocks

– Sector erase 64KB uniform granularity blocks

– Full-chip erase

• Write protection

– Software write protection applicable to every

64KB sector via volatile lock bit

– Hardware write protection: protected area size

defined by four nonvolatile bits (BP0, BP1, BP2,

and TB)

– Additional smart protections, available upon re-

quest

• Electronic signature

– JEDEC-standard, 2-byte signature (BA16h)

– Unique ID code: 17 read-only bytes, including:

• Two additional extended device ID bytes to

identify device factory options

• Customized factory data (14 bytes)

• Minimum 100,000 ERASE cycles per sector

• More than 20 years data retention

• Packages (JEDEC-standard, RoHS compliant)

– F4 = U-PDFN-8 4mm x 3mm (MLP8)

– F6 = V-PDFN-8 6mm x 5mm (MLP8)

– F8 = V-PDFN-8 8mm x 6mm (MLP8)

– 12 = T-PBGA-24b05 6mm x 8mm

– SC = SOP2-8 150 mils body width (SO8N)

– SF = SOP2-16 300 mils body width (SO16W)

– SE = SOP2-8 208 mils body width (SO8W)

•

PDF: 09005aef84566622

n25q_32mb_3v_65nm.pdf - Rev. J 2/15 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32Mb, 3V, Multiple I/O Serial Flash Memory

Features

Contents

Device Description ........................................................................................................................................... 6

Features ....................................................................................................................................................... 6

Operating Protocols ...................................................................................................................................... 6

XIP Mode ..................................................................................................................................................... 6

Device Configurability .................................................................................................................................. 7

Signal Assignments ........................................................................................................................................... 8

Signal Descriptions ......................................................................................................................................... 10

Memory Organization .................................................................................................................................... 12

Memory Configuration and Block Diagram .................................................................................................. 12

Memory Map – 32Mb Density ......................................................................................................................... 13

Device Protection ........................................................................................................................................... 14

Serial Peripheral Interface Modes .................................................................................................................... 16

SPI Protocols .................................................................................................................................................. 18

Nonvolatile and Volatile Registers ................................................................................................................... 19

Status Register ............................................................................................................................................ 20

Nonvolatile and Volatile Configuration Registers .......................................................................................... 22

Enhanced Volatile Configuration Register .................................................................................................... 24

Flag Status Register ..................................................................................................................................... 25

Command Definitions .................................................................................................................................... 27

READ REGISTER and WRITE REGISTER Operations ........................................................................................ 29

READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 29

READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 29

READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 30

WRITE STATUS REGISTER Command ......................................................................................................... 30

WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 31

WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 31

READ LOCK REGISTER Command .............................................................................................................. 32

WRITE LOCK REGISTER Command ............................................................................................................ 33

CLEAR FLAG STATUS REGISTER Command ................................................................................................ 34

READ IDENTIFICATION Operations ............................................................................................................... 35

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 35

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 36

READ MEMORY Operations ............................................................................................................................ 39

PROGRAM Operations .................................................................................................................................... 43

WRITE Operations .......................................................................................................................................... 48

WRITE ENABLE Command ......................................................................................................................... 48

WRITE DISABLE Command ........................................................................................................................ 48

ERASE Operations .......................................................................................................................................... 50

SUBSECTOR ERASE Command ................................................................................................................... 50

SECTOR ERASE Command ......................................................................................................................... 50

BULK ERASE Command ............................................................................................................................. 51

PROGRAM/ERASE SUSPEND Command ..................................................................................................... 52

PROGRAM/ERASE RESUME Command ...................................................................................................... 54

ONE TIME PROGRAMMABLE Operations ....................................................................................................... 55

READ OTP ARRAY Command ...................................................................................................................... 55

PROGRAM OTP ARRAY Command .............................................................................................................. 55

XIP Mode ....................................................................................................................................................... 58

Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 58

Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 58

Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 59

PDF: 09005aef84566622

n25q_32mb_3v_65nm.pdf - Rev. J 2/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32Mb, 3V, Multiple I/O Serial Flash Memory

Features

Terminating XIP After a Controller and Memory Reset .................................................................................

Power-Up and Power-Down ............................................................................................................................

Power-Up and Power-Down Requirements ..................................................................................................

Power Loss Rescue Sequence ......................................................................................................................

AC Reset Specifications ...................................................................................................................................

Program and Erase Suspend Specifications ......................................................................................................

Absolute Ratings and Operating Conditions .....................................................................................................

DC Characteristics and Operating Conditions ..................................................................................................

AC Characteristics and Operating Conditions ..................................................................................................

Package Dimensions .......................................................................................................................................

Part Number Ordering Information .................................................................................................................

Revision History .............................................................................................................................................

Rev. J – 02/2015 ..........................................................................................................................................

Rev. I – 04/2013 ..........................................................................................................................................

Rev. H – 01/2013 .........................................................................................................................................

Rev. G – 09/2012 .........................................................................................................................................

Rev. F – 07/2012 ..........................................................................................................................................

Rev. E – 06/2012 ..........................................................................................................................................

Rev. D – 01/2012 .........................................................................................................................................

Rev. C – 10/2011 .........................................................................................................................................

Rev. B – 01/2011 .........................................................................................................................................

Rev. A – 05/2010 ..........................................................................................................................................

PDF: 09005aef84566622

n25q_32mb_3v_65nm.pdf - Rev. J 2/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32Mb, 3V, Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Logic Diagram ................................................................................................................................... 7

Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 8

Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8

Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9

Figure 5: Block Diagram ................................................................................................................................ 12

Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17

Figure 7: SPI Modes ....................................................................................................................................... 17

Figure 8: Internal Configuration Register ........................................................................................................ 19

Figure 9: READ REGISTER Command ............................................................................................................ 29

Figure 10: WRITE REGISTER Command ......................................................................................................... 31

Figure 11: READ LOCK REGISTER Command ................................................................................................. 33

Figure 12: WRITE LOCK REGISTER Command ............................................................................................... 34

Figure 13: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 36

Figure 14: READ Command ........................................................................................................................... 40

Figure 15: FAST READ Command ................................................................................................................... 40

Figure 16: DUAL OUTPUT FAST READ ........................................................................................................... 41

Figure 17: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 41

Figure 18: QUAD OUTPUT FAST READ Command ......................................................................................... 42

Figure 19: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 42

Figure 20: PAGE PROGRAM Command .......................................................................................................... 44

Figure 21: DUAL INPUT FAST PROGRAM Command ...................................................................................... 45

Figure 22: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 45

Figure 23: QUAD INPUT FAST PROGRAM Command ..................................................................................... 46

Figure 24: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 47

Figure 25: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 49

Figure 26: SUBSECTOR and SECTOR ERASE Command .................................................................................. 51

Figure 27: BULK ERASE Command ................................................................................................................ 52

Figure 28: READ OTP Command .................................................................................................................... 55

Figure 29: PROGRAM OTP Command ............................................................................................................ 57

Figure 30: XIP Mode Directly After Power-On .................................................................................................. 59

Figure 31: Power-Up Timing .......................................................................................................................... 61

Figure 32: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 64

Figure 33: Serial Input Timing ........................................................................................................................ 64

Figure 34: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 65

Figure 35: Hold Timing .................................................................................................................................. 66

Figure 36: Output Timing .............................................................................................................................. 67

Figure 37: V

PPH

Timing .................................................................................................................................. 67

Figure 38: AC Timing Input/Output Reference Levels ...................................................................................... 70

Figure 39: U-PDFN-8 4mm x 3mm (MLP8) – Package Code: F4 ........................................................................ 74

Figure 40: V-PDFN-8 6mm x 5mm (MLP8) – Package Code: F6 ........................................................................ 75

Figure 41: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 76

Figure 42: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 77

Figure 43: SOP2-8 (150 mils body width) – Package Code: SC ........................................................................... 78

Figure 44: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 79

Figure 45: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 80

PDF: 09005aef84566622

n25q_32mb_3v_65nm.pdf - Rev. J 2/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

32Mb, 3V, Multiple I/O Serial Flash Memory

Features

List of Tables

Table 1: Signal Descriptions ...........................................................................................................................

Table 2: Sectors[63:0] .....................................................................................................................................

Table 3: Data Protection using Device Protocols .............................................................................................

Table 4: Memory Sector Protection Truth Table ..............................................................................................

Table 5: Protected Area Sizes – Upper Area .....................................................................................................

Table 6: Protected Area Sizes – Lower Area ......................................................................................................

Table 7: SPI Modes ........................................................................................................................................

Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................

Table 9: Status Register Bit Definitions ...........................................................................................................

Table 10: Nonvolatile Configuration Register Bit Definitions ...........................................................................

Table 11: Volatile Configuration Register Bit Definitions ..................................................................................

Table 12: Sequence of Bytes During Wrap .......................................................................................................

Table 13: Supported Clock Frequencies ..........................................................................................................

Table 14: Enhanced Volatile Configuration Register Bit Definitions ..................................................................

Table 15: Flag Status Register Bit Definitions ..................................................................................................

Table 16: Command Set .................................................................................................................................

Table 17: Lock Register ..................................................................................................................................

Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands .......................................

Table 19: Read ID Data Out ............................................................................................................................

Table 20: Extended Device ID, First Byte .........................................................................................................

Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................

Table 22: Parameter ID ..................................................................................................................................

Table 23: Command/Address/Data Lines for READ MEMORY Commands .......................................................

Table 24: Data/Address Lines for PROGRAM Commands ................................................................................

Table 25: Operations Allowed/Disallowed During Device States ......................................................................

Table 26: OTP Control Byte (Byte 64) ..............................................................................................................

Table 27: XIP Confirmation Bit .......................................................................................................................

Table 28: Effects of Running XIP in Different Protocols ....................................................................................

Table 29: Power-Up Timing and V

Threshold ...............................................................................................

Table 30: AC RESET Conditions ......................................................................................................................

Table 31: Suspend Parameters .......................................................................................................................

Table 32: Absolute Ratings .............................................................................................................................

Table 33: Operating Conditions ......................................................................................................................

Table 34: Input/Output Capacitance ..............................................................................................................

Table 35: AC Timing Input/Output Conditions ...............................................................................................

Table 36: DC Current Characteristics and Operating Conditions ......................................................................

Table 37: DC Voltage Characteristics and Operating Conditions ......................................................................

Table 38: AC Characteristics and Operating Conditions ...................................................................................

Table 39: Part Number Information ................................................................................................................

Table 40: Package Details ...............................................................................................................................

PDF: 09005aef84566622

n25q_32mb_3v_65nm.pdf - Rev. J 2/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

N25Q032A13EF4A0F

N25Q032A13EF4A0F在线购买

N25Q032A13EF4A0F概述

N25Q032A13EF4A0F规格参数

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